| Line 2... |
Line 2... |
--| Modular Oscilloscope
|
--| Modular Oscilloscope
|
--| UNSL - Argentine
|
--| UNSL - Argentine
|
--|
|
--|
|
--| File: eppwbn_test.vhd
|
--| File: eppwbn_test.vhd
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--| Version: 0.60
|
--| Version: 0.60
|
--| Tested in: Actel APA300, Actel A3PE1500
|
--| Tested in: Actel APA300
|
|
--| Tested in: Actel A3PE1500
|
|
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
--| Description:
|
--| Description:
|
--| EPP - Wishbone bridge.
|
--| EPP - Wishbone bridge.
|
--| This file is only for test purposes
|
--| This file is only for test purposes
|
--|
|
--|
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
--| File history:
|
--| File history:
|
--| 0.10 | jan-2008 | First release
|
--| 0.10 | jan-2008 | First release
|
--| 0.50 | jun-2009 | Sample testing signals
|
--| 0.50 | jun-2009 | Testing signals
|
--| 0.60 | jun-2009 | Sample testing instance for a dual port memory
|
--| 0.60 | jun-2009 | Testing instance for the dual port memory
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
--| Copyright ® 2008, Facundo Aguilera.
|
--| Copyright ® 2008, Facundo Aguilera.
|
--|
|
--|
|
--| This VHDL design file is an open design; you can redistribute it and/or
|
--| This VHDL design file is an open design; you can redistribute it and/or
|
--| modify it and/or implement it after contacting the author.
|
--| modify it and/or implement it after contacting the author.
|
