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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_16bit_test_wb_side.vhd] - Diff between revs 19 and 22
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Rev 22 |
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.eppwbn_pgk.all;
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use work.eppwbn_pkg.all;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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entity eppwbn_16bit_test_wb_side is
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entity eppwbn_16bit_test_wb_side is
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port(
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port(
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (WIDTH-1 downto 0);
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DAT_I: in std_logic_vector (WIDTH-1 downto 0);
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DAT_O: out std_logic_vector (WIDTH-1 downto 0);
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DAT_O: out std_logic_vector (WIDTH-1 downto 0);
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ADR_I: in std_logic_vector (7 downto 0);
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ADR_I: in std_logic_vector (ADD_WIDTH-1 downto 0);
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CYC_I: in std_logic;
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CYC_I: in std_logic;
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STB_I: in std_logic;
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STB_I: in std_logic;
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ACK_O: out std_logic ;
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ACK_O: out std_logic ;
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WE_I: in std_logic
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WE_I: in std_logic
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);
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);
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begin
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begin
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MEM1: test_memory
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MEM1: test_memory
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generic map(
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generic map(
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DEFAULT_OUT => '0',
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DEFAULT_OUT => '0',
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ADD_WIDTH => 8,
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ADD_WIDTH => ADD_WIDTH,
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WIDTH => WIDTH
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WIDTH => WIDTH
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)
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)
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port map (
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port map (
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cs => auto_ack,
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cs => auto_ack,
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clk => CLK_I,
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clk => CLK_I,
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