| Line 1... |
Line 1... |
--|------------------------------------------------------------------------------
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--|------------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--|
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--|
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--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
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--| Version: 0.10
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--| Version: 0.20
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--| Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This module controls the negotiation (IEEE Std. 1284-2000).
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--| This module controls the negotiation (IEEE Std. 1284-2000).
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--| This can be easily modified to control other modes besides the EPP.
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--| This can be easily modified to control other modes besides the EPP.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | nov-2008 | First testing release
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--| 0.01 | nov-2008 | First testing release
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--| 0.10 | dic-2008 | Customs signals without tri-state
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--| 0.20 | dic-2008 | Customs signals without tri-state
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--| 0.21 | jan-2009 | Asinc RST_I for Wishbone compatibility
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| Copyright Facundo Aguilera 2008
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--| Copyright ® 2008, Facundo Aguilera.
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--| GPL
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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|
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entity eppwbn_ctrl is
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entity eppwbn_ctrl is
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| Line 85... |
Line 88... |
ext_req_val <= Data;
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ext_req_val <= Data;
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end if;
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end if;
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end process P_data_store;
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end process P_data_store;
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- selección de estado siguiente
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-- estado siguiente
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P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin
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P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin
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|
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if RST_I = '1' then
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PError <= '-';
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nFault <= '-';
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Sel <= '-';
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nAck <= '-';
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epp_mode <= "--";
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next_state <= st_compatibility_idle;
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else
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case present_state is
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case present_state is
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when st_compatibility_idle =>
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when st_compatibility_idle =>
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PError <= '0';
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PError <= '0';
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nFault <= '1';
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nFault <= '1';
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| Line 171... |
Line 165... |
-- Finalizaci?n del modo EPP
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-- Finalizaci?n del modo EPP
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|
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next_state <= st_epp_mode;
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next_state <= st_epp_mode;
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-- Se sale de este estado en forma asíncrona ya que esta acción
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-- Se sale de este estado en forma asíncrona ya que esta acción
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end case; -- no tiene handshake.
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end case; -- no tiene handshake.
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end if;
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end process P_state_comb;
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end process P_state_comb;
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- establecimiento de estado actual
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-- estado actual
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P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
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P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
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if (nInit = '0' and nSelectIn = '0') then
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if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
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present_state <= st_compatibility_idle;
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present_state <= st_compatibility_idle;
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elsif present_state = st_epp_mode and nInit = '0' then
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elsif present_state = st_epp_mode and nInit = '0' then
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present_state <= st_compatibility_idle;
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present_state <= st_compatibility_idle;
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elsif (CLK_I'event and CLK_I='1') then
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elsif (CLK_I'event and CLK_I='1') then
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present_state <= next_state;
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present_state <= next_state;
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