| Line 85... |
Line 85... |
-- almacenamiento de Extensibility Request Value (asíncrono)
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-- almacenamiento de Extensibility Request Value (asíncrono)
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P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn)
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P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn)
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begin
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begin
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if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
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if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
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ext_req_val <= (others => '0');
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ext_req_val <= (others => '0');
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elsif (present_state = st_negotiation2 and nStrobe = '0') then
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elsif (nStrobe = '0') and present_state = st_negotiation2 then
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ext_req_val <= Data;
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ext_req_val <= Data;
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else
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ext_req_val <= ext_req_val;
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end if;
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end if;
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end process P_data_store;
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end process P_data_store;
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- estado siguiente
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-- estado siguiente
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| Line 186... |
Line 188... |
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- estado actual
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-- estado actual
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P_state_clocked: process(CLK_I, nInit, nSelectIn,RST_I) begin
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P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
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-- if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
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-- if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
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-- present_state <= st_compatibility_idle;
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-- present_state <= st_compatibility_idle;
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-- elsif present_state = st_epp_mode and nInit = '0' then
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-- elsif present_state = st_epp_mode and nInit = '0' then
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-- present_state <= st_compatibility_idle;
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-- present_state <= st_compatibility_idle;
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-- elsif (CLK_I'event and CLK_I='1') then
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-- elsif (CLK_I'event and CLK_I='1') then
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-- present_state <= next_state;
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-- present_state <= next_state;
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-- end if;
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-- end if;
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if (nInit = '0' and nSelectIn = '0') or RST_I = '1' then
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if (nInit = '0' and nSelectIn = '0') then
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present_state <= st_compatibility_idle;
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present_state <= st_compatibility_idle;
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elsif (CLK_I'event and CLK_I='1') then
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elsif (CLK_I'event and CLK_I='1') then
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present_state <= next_state;
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present_state <= next_state;
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end if;
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end if;
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end process P_state_clocked;
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end process P_state_clocked;
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