| Line 14... |
Line 14... |
--| File history:
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--| File history:
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--| 0.01 | nov-2008 | First testing release
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--| 0.01 | nov-2008 | First testing release
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--| 0.20 | dic-2008 | Custom signals without tri-state
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--| 0.20 | dic-2008 | Custom signals without tri-state
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--| 0.21 | jan-2009 | Sinc reset
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--| 0.21 | jan-2009 | Sinc reset
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright © 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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| Line 42... |
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- HostLogicH: in std_logic; -- (Host Logic High)
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-- HostLogicH: in std_logic; -- (Host Logic High)
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-- i indica misma señal de salida al puerto, aunque interna en el core y controlada por el bloque de control
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-- salida a la interface wishbone
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-- salida a la interface wishbone
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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