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Line 1... |
--------------------------------------------------------------------------------
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--|------------------------------------------------------------------------------
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-- UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--
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--|
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-- File: eppwbn_wbn_side.vhd
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--| File: eppwbn_epp_side.vhd
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-- Version: 0.01
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--| Version: 0.01
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-- Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--------------------------------------------------------------------------------
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--|------------------------------------------------------------------------------
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-- Description:
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--| Description:
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-- EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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-- EPP module output control (IEEE Std. 1284-2000).
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--| EPP module output control (IEEE Std. 1284-2000).
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File history:
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--| File history:
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-- 0.01 | nov-2008 | First release
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--| 0.01 | nov-2008 | First release
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright Facundo Aguilera 2008
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--| Copyright ® 2008, Facundo Aguilera.
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-- GPL
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Este fichero debe ser modificado ante casi cualquier modificaci?n de la arquitectura.
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entity eppwbn_epp_side is
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entity eppwbn_epp_side is
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port(
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port(
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-- Selección de modo
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-- Selección de modo
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epp_mode: in std_logic_vector (1 downto 0);-- indicador de modo de comunicaci?n epp
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epp_mode: in std_logic_vector (1 downto 0);-- indicador de modo de comunicación epp
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-- "00" deshabilitado
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-- "00" deshabilitado
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-- "01" inicial (señales de usuario e interrupciones deshabilitadas)
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-- "01" inicial (señales de usuario e interrupciones deshabilitadas)
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-- "10" sin definir
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-- "10" sin definir
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-- "11" modo EPP normal
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-- "11" modo EPP normal
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| Line 44... |
Line 44... |
-- WB-side signals
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-- WB-side signals
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wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait
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wb_Busy: in std_logic; -- PtrBusy/PeriphAck/nWait
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wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
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wb_nAutoFd: out std_logic; -- HostBusy/HostAck/nDStrb
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wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb
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wb_nSelectIn: out std_logic; -- 1284 Active/nAStrb
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wb_nStrobe: out std_logic; -- HostClk/nWrite
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wb_nStrobe: out std_logic; -- HostClk/nWrite
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-- No están implementadas las se?ales personalizadas
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-- No están implementadas las señales personalizadas
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-- To EPP port
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-- To EPP port
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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| Line 73... |
Line 73... |
ctr_nAutoFd <= nAutoFd;
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ctr_nAutoFd <= nAutoFd;
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ctr_nSelectIn <= nSelectIn;
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ctr_nSelectIn <= nSelectIn;
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ctr_nStrobe <= nStrobe;
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ctr_nStrobe <= nStrobe;
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-- Selección de salidas desde el módulo EPP cuando epp_mode = "11"
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-- Selección de salidas desde el módulo EPP cuando epp_mode = "11"
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-- Como no están implementadas las se?ales personalizadas se escribe "0000"
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-- Como no están implementadas las señales personalizadas se escribe "0000"
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multiplexing: process (epp_mode ,ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault,
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multiplexing: process (epp_mode ,ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault,
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nAutoFd, nSelectIn, nStrobe) begin
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nAutoFd, nSelectIn, nStrobe) begin
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case epp_mode is
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case epp_mode is
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when "11" =>
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when "11" =>
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