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--|-----------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--|
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--|
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--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
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--| Version: 0.10
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--| Version: 0.2
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--| Targeted device: Actel A3PE1500
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--| Tested in: Actel APA300
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--|-----------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| Package for instantiate all EPP-WBN modules.
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--| Package for instantiate all EPP-WBN modules.
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--------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First release
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--| 0.01 | dic-2008 | First release
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--| 0.10 | jan-2008 | Added testing memory
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--| 0.10 | jan-2009 | Added testing memory
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--------------------------------------------------------------------------------
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--| 0.20 | mar-2009 | Added extension module
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--| 0.30 | apr-2009 | Added pll
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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-- El módulo PLL solo funcionará con FPGAs de Actel
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-- Bloque completo
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-- Bloque completo
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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package eppwbn_pgk is
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package eppwbn_pgk is
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------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Componentes
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-- Componentes
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-- Bridge control
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-- Bridge control
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component eppwbn_ctrl is
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component eppwbn_ctrl is
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port(
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port(
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| Line 93... |
Line 98... |
rst_pp: in std_logic
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rst_pp: in std_logic
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);
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);
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end component eppwbn_wbn_side;
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end component eppwbn_wbn_side;
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-- Testing memory
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-- Testing memory
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component mem_8bit_reset is
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component test_memory is
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generic ( --USE_RESET : boolean := false; -- use system reset
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generic ( --USE_RESET : boolean := false; -- use system reset
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--USE_CS : boolean := false; -- use chip select signal
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--USE_CS : boolean := false; -- use chip select signal
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DEFAULT_OUT : std_logic := '0'; -- Default output
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DEFAULT_OUT : std_logic; -- Default output
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--OPTION : integer := 1; -- 1: Registered read Address(suitable
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--OPTION : integer := 1; -- 1: Registered read Address(suitable
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-- for Altera's FPGAs
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-- for Altera's FPGAs
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-- 0: non registered read address
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-- 0: non registered read address
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ADD_WIDTH : integer := 8;
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ADD_WIDTH : integer;
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WIDTH : integer := 8);
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WIDTH : integer);
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port (
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port (
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cs : in std_logic; -- chip select
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cs : in std_logic; -- chip select
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clk : in std_logic; -- write clock
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clk : in std_logic; -- write clock
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reset : in std_logic; -- System Reset
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reset : in std_logic; -- System Reset
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add : in std_logic_vector(add_width -1 downto 0); -- Address
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add : in std_logic_vector(add_width -1 downto 0); -- Address
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Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
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Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
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Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
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Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
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WR : in std_logic); -- Read Write Enable
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WR : in std_logic); -- Read Write Enable
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end component mem_8bit_reset;
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end component test_memory;
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-- Epp-wishbone bridge
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component eppwbn is
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component eppwbn is
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port(
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port(
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-- Externo
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-- Externo
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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nStrobe: in std_logic; -- HostClk/nWrite
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-- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select)
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Sel: out std_logic; -- XFlag (Select)
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| Line 144... |
Line 149... |
ACK_I: in std_logic ;
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ACK_I: in std_logic ;
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WE_O: out std_logic
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WE_O: out std_logic
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);
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);
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end component eppwbn;
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end component eppwbn;
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-- Testing component
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component eppwbn_test_wb_side is
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component eppwbn_test_wb_side is
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port(
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port(
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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| Line 158... |
Line 164... |
ACK_O: out std_logic ;
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ACK_O: out std_logic ;
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WE_I: in std_logic
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WE_I: in std_logic
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);
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);
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end component eppwbn_test_wb_side;
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end component eppwbn_test_wb_side;
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end package eppwbn_pgk;
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-- Width extension
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component eppwbn_width_extension is
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generic (
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TIME_OUT_VALUE: integer;
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TIME_OUT_WIDTH: integer
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);
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port(
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-- Slave signals
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DAT_I_sl: in std_logic_vector (7 downto 0);
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DAT_O_sl: out std_logic_vector (7 downto 0);
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ADR_I_sl: in std_logic_vector (7 downto 0);
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CYC_I_sl: in std_logic;
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STB_I_sl: in std_logic;
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ACK_O_sl: out std_logic ;
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WE_I_sl: in std_logic;
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-- Master signals
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DAT_I_ma: in std_logic_vector (15 downto 0);
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DAT_O_ma: out std_logic_vector (15 downto 0);
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ADR_O_ma: out std_logic_vector (7 downto 0);
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CYC_O_ma: out std_logic;
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STB_O_ma: out std_logic;
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ACK_I_ma: in std_logic ;
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WE_O_ma: out std_logic;
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-- Common signals
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RST_I: in std_logic;
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CLK_I: in std_logic
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);
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end component eppwbn_width_extension;
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component eppwbn_16bit is
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port(
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-- Externo
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nStrobe: in std_logic; -- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select)
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- Interno
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RST_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (15 downto 0);
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DAT_O: out std_logic_vector (15 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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CYC_O: out std_logic;
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STB_O: out std_logic;
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ACK_I: in std_logic ;
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WE_O: out std_logic
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);
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end component eppwbn_16bit;
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component eppwbn_16bit_test is
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port(
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-- al puerto EPP
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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-- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select)
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- a los switches
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rst: in std_logic;
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-- al clock
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clk: in std_logic
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);
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end component eppwbn_16bit_test;
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component eppwbn_16bit_test_wb_side is
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generic (
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ADD_WIDTH : integer ;
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WIDTH : integer
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);
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port(
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RST_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (WIDTH-1 downto 0);
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DAT_O: out std_logic_vector (WIDTH-1 downto 0);
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ADR_I: in std_logic_vector (7 downto 0);
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CYC_I: in std_logic;
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STB_I: in std_logic;
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ACK_O: out std_logic ;
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WE_I: in std_logic
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);
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end component eppwbn_16bit_test_wb_side;
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-- Clock (Actel specific)
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component pll is
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port(GLB, LOCK : out std_logic; CLK : in std_logic) ;
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end component pll;
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end package eppwbn_pgk;
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No newline at end of file
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No newline at end of file
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