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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First release
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--| 0.01 | dic-2008 | First release
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--| 0.10 | jan-2009 | Added testing memory
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--| 0.10 | jan-2009 | Added testing memory
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--| 0.20 | mar-2009 | Added extension module
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--| 0.20 | mar-2009 | Added extension module
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--| 0.30 | apr-2009 | Added pll
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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-- El módulo PLL solo funcionará con FPGAs de Actel
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-- Bloque completo
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-- Bloque completo
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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package eppwbn_pgk is
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package eppwbn_pkg is
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Componentes
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-- Componentes
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-- Bridge control
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-- Bridge control
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component eppwbn_ctrl is
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component eppwbn_ctrl is
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| Line 123... |
Line 120... |
end component test_memory;
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end component test_memory;
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-- Epp-wishbone bridge
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-- Epp-wishbone bridge
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component eppwbn is
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component eppwbn is
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port(
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port(
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-- TEMPORAL
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epp_mode_monitor: out std_logic_vector (1 downto 0);
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-- Externo
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-- Externo
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nStrobe: in std_logic; -- HostClk/nWrite
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nStrobe: in std_logic; -- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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| Line 199... |
Line 199... |
);
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);
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end component eppwbn_width_extension;
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end component eppwbn_width_extension;
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component eppwbn_16bit is
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component eppwbn_16bit is
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port(
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port(
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-- TEMPORAL
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epp_mode_monitor: out std_logic_vector (1 downto 0);
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-- Externo
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-- Externo
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nStrobe: in std_logic; -- HostClk/nWrite
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nStrobe: in std_logic; -- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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| Line 246... |
Line 249... |
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-- a los switches
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-- a los switches
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rst: in std_logic;
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rst: in std_logic;
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-- al clock
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-- al clock
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clk: in std_logic
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clk: in std_logic;
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-- monitores
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data_monitor: out std_logic_vector (7 downto 0);
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epp_mode_monitor: out std_logic_vector (1 downto 0)
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);
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);
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end component eppwbn_16bit_test;
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end component eppwbn_16bit_test;
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component eppwbn_16bit_test_wb_side is
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component eppwbn_16bit_test_wb_side is
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| Line 270... |
Line 277... |
WE_I: in std_logic
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WE_I: in std_logic
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);
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);
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end component eppwbn_16bit_test_wb_side;
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end component eppwbn_16bit_test_wb_side;
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-- Clock (Actel specific)
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-- Clock (Actel specific)
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component pll is
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component A3PE_pll is
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port(GLB, LOCK : out std_logic; CLK : in std_logic) ;
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port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out
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end component pll;
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std_logic) ;
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end component A3PE_pll;
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component dual_port_memory_wb is
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port(
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-- Puerto A (Higer prioriry)
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RST_I_a: in std_logic;
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CLK_I_a: in std_logic;
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DAT_I_a: in std_logic_vector (15 downto 0);
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DAT_O_a: out std_logic_vector (15 downto 0);
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ADR_I_a: in std_logic_vector (13 downto 0);
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CYC_I_a: in std_logic;
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STB_I_a: in std_logic;
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ACK_O_a: out std_logic ;
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WE_I_a: in std_logic;
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-- Puerto B (Lower prioriry)
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RST_I_b: in std_logic;
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CLK_I_b: in std_logic;
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DAT_I_b: in std_logic_vector (15 downto 0);
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DAT_O_b: out std_logic_vector (15 downto 0);
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ADR_I_b: in std_logic_vector (13 downto 0);
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CYC_I_b: in std_logic;
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STB_I_b: in std_logic;
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ACK_O_b: out std_logic ;
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WE_I_b: in std_logic
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);
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end component dual_port_memory_wb;
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end package eppwbn_pgk;
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end package eppwbn_pkg;
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No newline at end of file
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No newline at end of file
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