| Line 2... |
Line 2... |
--| UNSL - Modular Oscilloscope
|
--| UNSL - Modular Oscilloscope
|
--|
|
--|
|
--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
|
--| Version: 0.2
|
--| Version: 0.2
|
--| Tested in: Actel APA300
|
--| Tested in: Actel APA300
|
|
--| Tested in: Actel A3PE1500
|
|
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
--| Description:
|
--| Description:
|
--| EPP - Wishbone bridge.
|
--| EPP - Wishbone bridge.
|
--| Package for instantiate EPP-WBN modules.
|
--| Package for instantiate EPP-WBN modules.
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
| Line 122... |
Line 124... |
|
|
-- Epp-wishbone bridge
|
-- Epp-wishbone bridge
|
component eppwbn is
|
component eppwbn is
|
port(
|
port(
|
-- TEMPORAL
|
-- TEMPORAL
|
epp_mode_monitor: out std_logic_vector (1 downto 0);
|
--epp_mode_monitor: out std_logic_vector (1 downto 0);
|
|
|
-- Externo
|
-- Externo
|
nStrobe: in std_logic; -- HostClk/nWrite
|
nStrobe: in std_logic; -- HostClk/nWrite
|
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
|
Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
|
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
|
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
|
| Line 201... |
Line 203... |
end component eppwbn_width_extension;
|
end component eppwbn_width_extension;
|
|
|
component eppwbn_16bit is
|
component eppwbn_16bit is
|
port(
|
port(
|
-- TEMPORAL
|
-- TEMPORAL
|
epp_mode_monitor: out std_logic_vector (1 downto 0);
|
--epp_mode_monitor: out std_logic_vector (1 downto 0);
|
|
|
-- Externo
|
-- Externo
|
nStrobe: in std_logic; -- HostClk/nWrite
|
nStrobe: in std_logic; -- HostClk/nWrite
|
Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
|
Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
|
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
|
nAck: out std_logic; -- PtrClk/PeriphClk/Intr
|
