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Line 285... |
component A3PE_pll is
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component A3PE_pll is
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port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out
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port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out
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std_logic) ;
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std_logic) ;
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end component A3PE_pll;
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end component A3PE_pll;
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component dual_port_memory_wb is
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-- component dual_port_memory_wb is
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port(
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-- port(
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-- Puerto A (Higer prioriry)
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-- -- Puerto A (Higer prioriry)
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RST_I_a: in std_logic;
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-- RST_I_a: in std_logic;
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CLK_I_a: in std_logic;
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-- CLK_I_a: in std_logic;
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DAT_I_a: in std_logic_vector (15 downto 0);
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-- DAT_I_a: in std_logic_vector (15 downto 0);
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DAT_O_a: out std_logic_vector (15 downto 0);
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-- DAT_O_a: out std_logic_vector (15 downto 0);
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ADR_I_a: in std_logic_vector (13 downto 0);
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-- ADR_I_a: in std_logic_vector (13 downto 0);
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CYC_I_a: in std_logic;
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-- CYC_I_a: in std_logic;
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STB_I_a: in std_logic;
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-- STB_I_a: in std_logic;
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ACK_O_a: out std_logic ;
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-- ACK_O_a: out std_logic ;
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WE_I_a: in std_logic;
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-- WE_I_a: in std_logic;
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-- Puerto B (Lower prioriry)
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-- -- Puerto B (Lower prioriry)
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RST_I_b: in std_logic;
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-- RST_I_b: in std_logic;
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CLK_I_b: in std_logic;
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-- CLK_I_b: in std_logic;
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DAT_I_b: in std_logic_vector (15 downto 0);
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-- DAT_I_b: in std_logic_vector (15 downto 0);
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DAT_O_b: out std_logic_vector (15 downto 0);
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-- DAT_O_b: out std_logic_vector (15 downto 0);
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ADR_I_b: in std_logic_vector (13 downto 0);
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-- ADR_I_b: in std_logic_vector (13 downto 0);
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CYC_I_b: in std_logic;
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-- CYC_I_b: in std_logic;
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STB_I_b: in std_logic;
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-- STB_I_b: in std_logic;
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ACK_O_b: out std_logic ;
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-- ACK_O_b: out std_logic ;
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WE_I_b: in std_logic
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-- WE_I_b: in std_logic
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);
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-- );
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end component dual_port_memory_wb;
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-- end component dual_port_memory_wb;
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end package eppwbn_pkg;
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end package eppwbn_pkg;
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