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https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk
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Rev 19 |
| Line 45... |
Line 45... |
rst: in std_logic;
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rst: in std_logic;
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-- al clock
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-- al clock
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clk: in std_logic
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clk: in std_logic
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-- a los leds
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--epp_mode: out std_logic_vector(1 downto 0);
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--nAck_monitor: out std_logic;
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--busy_monitor: out std_logic;
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--PError_monitor: out std_logic;
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--Sel_monitor: out std_logic;
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--nFault_monitor: out std_logic;
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-- nAutoFd_monitor: out std_logic;
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-- nInit_monitor: out std_logic;
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-- nSelectIn_monitor: out std_logic;
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-- nStrobe_monitor: out std_logic
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--PeriphLogicH_monitor: out std_logic;
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);
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);
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end eppwbn_test;
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end eppwbn_test;
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architecture eppwbn_test_arch0 of eppwbn_test is
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architecture eppwbn_test_arch0 of eppwbn_test is
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Line 69... |
signal ADR_O_master: std_logic_vector (7 downto 0);
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signal ADR_O_master: std_logic_vector (7 downto 0);
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signal CYC_O_master: std_logic;
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signal CYC_O_master: std_logic;
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signal STB_O_master: std_logic;
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signal STB_O_master: std_logic;
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signal ACK_I_master: std_logic;
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signal ACK_I_master: std_logic;
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signal WE_O_master: std_logic;
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signal WE_O_master: std_logic;
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signal clk_pll: std_logic;
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begin
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begin
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SL_MEM1: eppwbn_test_wb_side port map(
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SL_MEM1: eppwbn_test_wb_side
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port map(
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RST_I => rst,
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RST_I => rst,
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CLK_I => clk,
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CLK_I => clk_pll,
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DAT_I => DAT_O_master,
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DAT_I => DAT_O_master,
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DAT_O => DAT_I_master,
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DAT_O => DAT_I_master,
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ADR_I => ADR_O_master,
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ADR_I => ADR_O_master,
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CYC_I => CYC_O_master,
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CYC_I => CYC_O_master,
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STB_I => STB_O_master,
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STB_I => STB_O_master,
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ACK_O => ACK_I_master,
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ACK_O => ACK_I_master,
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WE_I => WE_O_master
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WE_I => WE_O_master
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);
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);
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MA_EPP: eppwbn port map(
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MA_EPP: eppwbn port map(
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-- Externo
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-- Externo
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nStrobe => nStrobe,
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nStrobe => nStrobe,
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Data => Data,
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Data => Data,
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nAck => nAck,
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nAck => nAck,
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| Line 87... |
Line 103... |
nInit => nInit,
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nInit => nInit,
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nFault => nFault,
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nFault => nFault,
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nSelectIn => nSelectIn,
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nSelectIn => nSelectIn,
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-- Interno
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-- Interno
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RST_I => rst,
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RST_I => rst,
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CLK_I => clk,
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CLK_I => clk_pll,
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DAT_I => DAT_I_master,
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DAT_I => DAT_I_master,
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DAT_O => DAT_O_master,
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DAT_O => DAT_O_master,
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ADR_O => ADR_O_master,
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ADR_O => ADR_O_master,
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CYC_O => CYC_O_master,
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CYC_O => CYC_O_master,
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STB_O => STB_O_master,
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STB_O => STB_O_master,
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ACK_I => ACK_I_master,
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ACK_I => ACK_I_master,
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WE_O => WE_O_master
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WE_O => WE_O_master
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);
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);
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PLL_0: pll port map(
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GLB => clk_pll,
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CLK => clk
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);
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end architecture eppwbn_test_arch0;
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end architecture eppwbn_test_arch0;
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