URL
https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 16 |
Rev 19 |
| Line 45... |
Line 45... |
rst: in std_logic;
|
rst: in std_logic;
|
|
|
-- al clock
|
-- al clock
|
clk: in std_logic
|
clk: in std_logic
|
|
|
|
-- a los leds
|
|
--epp_mode: out std_logic_vector(1 downto 0);
|
|
--nAck_monitor: out std_logic;
|
|
--busy_monitor: out std_logic;
|
|
--PError_monitor: out std_logic;
|
|
--Sel_monitor: out std_logic;
|
|
--nFault_monitor: out std_logic;
|
|
-- nAutoFd_monitor: out std_logic;
|
|
-- nInit_monitor: out std_logic;
|
|
-- nSelectIn_monitor: out std_logic;
|
|
-- nStrobe_monitor: out std_logic
|
|
--PeriphLogicH_monitor: out std_logic;
|
);
|
);
|
end eppwbn_test;
|
end eppwbn_test;
|
|
|
architecture eppwbn_test_arch0 of eppwbn_test is
|
architecture eppwbn_test_arch0 of eppwbn_test is
|
|
|
| Line 57... |
Line 69... |
signal ADR_O_master: std_logic_vector (7 downto 0);
|
signal ADR_O_master: std_logic_vector (7 downto 0);
|
signal CYC_O_master: std_logic;
|
signal CYC_O_master: std_logic;
|
signal STB_O_master: std_logic;
|
signal STB_O_master: std_logic;
|
signal ACK_I_master: std_logic;
|
signal ACK_I_master: std_logic;
|
signal WE_O_master: std_logic;
|
signal WE_O_master: std_logic;
|
|
signal clk_pll: std_logic;
|
|
|
begin
|
begin
|
|
|
SL_MEM1: eppwbn_test_wb_side port map(
|
SL_MEM1: eppwbn_test_wb_side
|
|
port map(
|
RST_I => rst,
|
RST_I => rst,
|
CLK_I => clk,
|
CLK_I => clk_pll,
|
DAT_I => DAT_O_master,
|
DAT_I => DAT_O_master,
|
DAT_O => DAT_I_master,
|
DAT_O => DAT_I_master,
|
ADR_I => ADR_O_master,
|
ADR_I => ADR_O_master,
|
CYC_I => CYC_O_master,
|
CYC_I => CYC_O_master,
|
STB_I => STB_O_master,
|
STB_I => STB_O_master,
|
ACK_O => ACK_I_master,
|
ACK_O => ACK_I_master,
|
WE_I => WE_O_master
|
WE_I => WE_O_master
|
);
|
);
|
|
|
|
|
|
|
MA_EPP: eppwbn port map(
|
MA_EPP: eppwbn port map(
|
-- Externo
|
-- Externo
|
nStrobe => nStrobe,
|
nStrobe => nStrobe,
|
Data => Data,
|
Data => Data,
|
nAck => nAck,
|
nAck => nAck,
|
| Line 87... |
Line 103... |
nInit => nInit,
|
nInit => nInit,
|
nFault => nFault,
|
nFault => nFault,
|
nSelectIn => nSelectIn,
|
nSelectIn => nSelectIn,
|
-- Interno
|
-- Interno
|
RST_I => rst,
|
RST_I => rst,
|
CLK_I => clk,
|
CLK_I => clk_pll,
|
DAT_I => DAT_I_master,
|
DAT_I => DAT_I_master,
|
DAT_O => DAT_O_master,
|
DAT_O => DAT_O_master,
|
ADR_O => ADR_O_master,
|
ADR_O => ADR_O_master,
|
CYC_O => CYC_O_master,
|
CYC_O => CYC_O_master,
|
STB_O => STB_O_master,
|
STB_O => STB_O_master,
|
ACK_I => ACK_I_master,
|
ACK_I => ACK_I_master,
|
WE_O => WE_O_master
|
WE_O => WE_O_master
|
);
|
);
|
|
|
|
PLL_0: pll port map(
|
|
GLB => clk_pll,
|
|
CLK => clk
|
|
);
|
|
|
end architecture eppwbn_test_arch0;
|
end architecture eppwbn_test_arch0;
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.