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--| It only stores data in regiters with wishbone interconect
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--| It only stores data in regiters with wishbone interconect
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--| File history:
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--| File history:
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--| 0.10 | dic-2008 | First release
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--| 0.10 | dic-2008 | First release
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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architecture eppwbn_test_wb_arch0 of eppwbn_test_wb_side is
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architecture eppwbn_test_wb_arch0 of eppwbn_test_wb_side is
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signal auto_ack: std_logic;
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signal auto_ack: std_logic;
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begin
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begin
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MEM1: mem_8bit_reset
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MEM1: test_memory
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generic map(
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DEFAULT_OUT => '0';
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ADD_WIDTH => 8;
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WIDTH => 8
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port map (
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port map (
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cs => auto_ack,
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cs => auto_ack,
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clk => CLK_I,
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clk => CLK_I,
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reset => RST_I,
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reset => RST_I,
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add => ADR_I,
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add => ADR_I,
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