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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_test_wb_side.vhd] - Diff between revs 19 and 22

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Rev 19 Rev 22
Line 11... Line 11... 
--|   It only stores data in regiters with wishbone interconect
 
--|   It only stores data in regiters with wishbone interconect
 
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--| File history:
 
--| File history:
 
--|   0.10   | dic-2008 | First release
 
--|   0.10   | dic-2008 | First release
 
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--| Copyright ® 2008, Facundo Aguilera.
 
--| Copyright ® 2008, Facundo Aguilera.
 
--|
 
--|
 
--| This VHDL design file is an open design; you can redistribute it and/or
 
--| This VHDL design file is an open design; you can redistribute it and/or
 
--| modify it and/or implement it after contacting the author.
 
--| modify it and/or implement it after contacting the author.
 
 
 
 
 
 
 
 
 
library IEEE;
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_1164.ALL;
 
use work.eppwbn_pgk.all;
 
use work.eppwbn_pkg.all;
 
--use IEEE.STD_LOGIC_ARITH.ALL;
 
--use IEEE.STD_LOGIC_ARITH.ALL;
 
 
 
 
 
 
 
 
 
entity eppwbn_test_wb_side is
 
entity eppwbn_test_wb_side is
 
  port(
 
  port(

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