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----------------------------------------------------------------------------------------------------
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
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--| Version: 0.2
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--| Version: 0.5
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--| Tested in: Actel APA300
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--| Tested in: Actel APA300
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This module is in the wishbone side (IEEE Std. 1284-2000).
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--| This module is in the wishbone side (IEEE Std. 1284-2000).
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | nov-2008 | First release
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--| 0.01 | nov-2008 | First release
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--| 0.1 | jan-2009 | Sinc reset
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--| 0.1 | jan-2009 | Sinc reset
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--| 0.2 | feb-2009 | Some improvements
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--| 0.2 | feb-2009 | Some improvements
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--| 0.5 | sep-2009 | New design, full sincronous
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright © 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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entity eppwbn_wbn_side is
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entity eppwbn_wbn_side is
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-- generic(
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-- WAIT_DELAY : integer := 4 -- min value: 3
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-- );
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port(
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port(
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-- al puerto epp
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-- Nomenclatura IEEE Std. 1284-2000
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-- Negotiation/ECP/EPP (Compatibiliy)
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inStrobe: in std_logic; -- HostClk/nWrite
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inStrobe: in std_logic; -- HostClk/nWrite
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iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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-- inAck: out std_logic; -- PtrClk/PeriphClk/Intr
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iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
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iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
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-- iPError: out std_logic; -- AckData/nAckReverse
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-- iSel: out std_logic; -- XFlag (Select)
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inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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-- iPeriphLogicH: out std_logic; -- (Periph Logic High)
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-- inInit: in std_logic; -- nReverseRequest
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-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- iHostLogicH: in std_logic; -- (Host Logic High)
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-- i indica interna en el core y controlada por el bloque de control
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-- a la interface wishbone
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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CYC_O: out std_logic;
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CYC_O: out std_logic;
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STB_O: out std_logic;
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STB_O: out std_logic;
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ACK_I: in std_logic ;
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ACK_I: in std_logic ;
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WE_O: out std_logic;
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WE_O: out std_logic;
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rst_pp: in std_logic -- reset from pp
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rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo
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);
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);
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end eppwbn_wbn_side;
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end eppwbn_wbn_side;
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architecture con_registro of eppwbn_wbn_side is
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architecture bridge2 of eppwbn_wbn_side is
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type StateType is (
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ST_IDLE,
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ST_ADDR,
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ST_WRITING_D1,
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ST_WRITING_D2,
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ST_READING_D1,
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ST_READING_D2
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);
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signal next_state, present_state: StateType;
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signal nWrite: std_logic;
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signal nWait: std_logic;
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signal nDStrb: std_logic;
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signal nAStrb: std_logic;
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signal strb_hist: std_logic_vector(4 downto 0);
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signal strb_ris: std_logic;
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signal strb_fall: std_logic;
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signal strb_wb: std_logic;
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signal ack_pp: std_logic;
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signal adr_ack,data_ack: std_logic;
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signal adr_reg,data_reg: std_logic_vector (7 downto 0); -- registros internos temporales
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signal adr_reg,data_reg: std_logic_vector (7 downto 0); -- registros internos temporales
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signal pre_STB_O: std_logic; -- registro que maneja a STB_O
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--signal waiting: std_logic_vector(WAIT_DELAY-1 downto 0);
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begin
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begin
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iBusy <= adr_ack or data_ack; -- nWait. Se utiliza para confirmación de lectura/escritura de datos/direcciones
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-- Equal
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WE_O <= not(inStrobe); -- Ambas señales tienen la misma utilidad, habilitan escritura
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nWrite <= inStrobe;
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STB_O <= pre_STB_O ;
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nAStrb <= inSelectIn;
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CYC_O <= pre_STB_O;
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nDStrb <= inAutoFd;
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DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos
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iBusy <= nWait;
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-- a wishbone, lectura y escritura de datos desde epp
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-- Data R/W
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STB_O <= strb_wb;
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data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp, data_ack,inStrobe,iData)
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CYC_O <= strb_wb;
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ADR_O <= adr_reg;
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DAT_O <= data_reg;
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-- Thanks fpga4fun
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P_strobes: process(nAStrb, nDStrb, CLK_I, strb_hist, RST_I, rst_pp)
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begin
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begin
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if CLK_I 'event and CLK_I = '1' then
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if RST_I = '1' or rst_pp = '1' then
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strb_hist <= (others => '1' );
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else
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strb_hist <= strb_hist(3 downto 0) & (nAStrb and nDStrb); -- only one is zero at a time
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end if;
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end if;
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end process;
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strb_ris <= '1' when strb_hist(4 downto 1) = "0111" else '0';
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strb_fall <= '1' when strb_hist(4 downto 1) = "0000" else '0';
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if (rst_pp = '1') then -- Reset de desde interfaz EPP asíncrono
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data_reg <= (others => '0');
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pre_STB_O <= '0';
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data_ack <= '0';
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elsif inAutoFd = '0' and data_ack = '0' and pre_STB_O = '0' then -- Data strobe
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P_next_st: process(strb_ris, strb_fall, ACK_I, nAStrb, nDStrb, nWrite, present_state)
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if (inStrobe = '0') then -- Escritura EPP
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begin
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data_reg <= iData;
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end if;
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pre_STB_O <= '1';
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elsif inAutoFd = '1' and data_ack = '1' then -- iBusy solo se pondrá a cero
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data_ack <= '0';
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-- Se indica el la comprobación de data_ack = '1' para forzar a la herramienta
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-- de síntesis a crear un registro.
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elsif (CLK_I'event and CLK_I = '1') then
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case present_state is
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if RST_I = '1' then
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when ST_ADDR =>
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data_reg <= (others => '0');
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strb_wb <= '0';
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pre_STB_O <= '0';
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ack_pp <= '1';
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data_ack <= '0';
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WE_O <= '0';
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-- >>> --
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if strb_ris = '1' then
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next_state <= ST_IDLE;
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else
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else
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if (ACK_I = '1' and pre_STB_O = '1') then -- Dato escrito o leído
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next_state <= present_state;
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pre_STB_O <= '0';
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data_ack <= '1';
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if (inStrobe = '1') then -- Lectura EPP
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data_reg <= DAT_I;
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end if;
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end if;
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end if;
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when ST_WRITING_D1 =>
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strb_wb <= '0';
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ack_pp <= '1';
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WE_O <= '0';
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-- >>> --
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if strb_ris = '1' then
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next_state <= ST_WRITING_D2;
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else
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next_state <= present_state;
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end if;
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end if;
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when ST_WRITING_D2 =>
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strb_wb <= '1';
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ack_pp <= '0';
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WE_O <= '1';
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-- >>> --
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if ACK_I = '1' then
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next_state <= ST_IDLE;
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else
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next_state <= present_state;
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end if;
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end if;
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when ST_READING_D1 =>
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strb_wb <= '1';
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ack_pp <= '0';
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WE_O <= '0';
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-- >>> --
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if strb_ris = '1' then
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next_state <= ST_IDLE;
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elsif ACK_I = '1' then
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next_state <= ST_READING_D2;
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else
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next_state <= present_state;
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end if;
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when ST_READING_D2 =>
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strb_wb <= '0';
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ack_pp <= '1';
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WE_O <= '0';
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-- >>> --
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if strb_ris = '1' then
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next_state <= ST_IDLE;
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else
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next_state <= present_state;
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end if;
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when others => -- ST_IDLE
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strb_wb <= '0';
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ack_pp <= '0';
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WE_O <= '0';
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-- >>> --
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if strb_fall = '1' then
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if nWrite = '0' and nDStrb = '0' then
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next_state <= ST_WRITING_D1;
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elsif nWrite = '1' and nDStrb = '0' then
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next_state <= ST_READING_D1;
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elsif nAStrb = '0' then
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next_state <= ST_ADDR;
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else
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next_state <= present_state;
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end if;
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else
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next_state <= present_state;
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end if;
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end case;
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end process;
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end process;
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P_act_st: process(CLK_I, RST_I, rst_pp, next_state, iData, DAT_I, present_state, nWrite)
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-- Adr R/W
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adr_ack <= not(inSelectIn); -- Autoconfirmación de estado.
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adr_strobing: process (inSelectIn, RST_I, rst_pp,inStrobe,iData)
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begin
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begin
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if (RST_I = '1' or rst_pp = '1') then
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if (CLK_I'event and CLK_I='1') then
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if RST_I = '1' or rst_pp = '1' then
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present_state <= ST_IDLE;
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data_reg <= (others => '0');
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adr_reg <= (others => '0');
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adr_reg <= (others => '0');
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elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
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else
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if inStrobe = '0' then
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present_state <= next_state;
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case present_state is
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when ST_ADDR =>
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--if next_state = ST_IDLE and nWrite = '0' then
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if strb_hist(0) = '0' and nWrite = '0' then
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adr_reg <= iData;
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adr_reg <= iData;
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end if;
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end if;
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when ST_WRITING_D1 =>
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--if next_state = ST_WRITING_D2 then
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if strb_hist(0) = '0' then
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data_reg <= iData;
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end if;
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when ST_READING_D1 =>
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if next_state = ST_READING_D2 then
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data_reg <= DAT_I;
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end if;
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when others =>
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end case;
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end if;
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end if;
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end if;
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end process;
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end process;
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ADR_O <= adr_reg;
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nWait <= ack_pp;
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-- Puerto bidireccional
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iData <= data_reg when (nWrite = '1' and nDStrb = '0' ) else
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iData <= data_reg when (inStrobe = '1' and data_ack = '1') else
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adr_reg when (nWrite = '1' and nAStrb = '0' ) else
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adr_reg when (inStrobe = '1' and adr_ack = '1') else
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(others => 'Z');
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(others => 'Z');
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-- P_delay: process(ack_pp, CLK_I, rst_pp, RST_I, waiting)
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-- begin
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-- if CLK_I'event and CLK_I = '1' then
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-- if rst_pp = '1' or RST_I = '1' then
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-- waiting <= (others => '0');
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-- else
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-- waiting <= waiting(WAIT_DELAY-2 downto 0) & ack_pp;
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-- end if;
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-- end if;
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-- end process;
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end con_registro;
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end architecture bridge2;
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