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--------------------------------------------------------------------------------
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--|------------------------------------------------------------------------------
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-- UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--
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--|
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-- File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
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-- Version: 0.20
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--| Version: 0.20
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-- Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--------------------------------------------------------------------------------
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--|------------------------------------------------------------------------------
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-- Description:
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--| Description:
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-- EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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-- This module is in the wishbone side (IEEE Std. 1284-2000).
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--| This module is in the wishbone side (IEEE Std. 1284-2000).
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File history:
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--| File history:
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-- 0.01 | nov-2008 | First release
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--| 0.01 | nov-2008 | First release
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright Facundo Aguilera 2008
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--| Copyright ® 2008, Facundo Aguilera.
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-- GPL
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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-- iPeriphLogicH: out std_logic; -- (Periph Logic High)
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-- iPeriphLogicH: out std_logic; -- (Periph Logic High)
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-- inInit: in std_logic; -- nReverseRequest
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-- inInit: in std_logic; -- nReverseRequest
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-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
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-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- iHostLogicH: in std_logic; -- (Host Logic High)
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-- iHostLogicH: in std_logic; -- (Host Logic High)
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-- i indica misma señal de salida al puerto, aunque interna en el core y controlada por el bloque de control
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-- i indica interna en el core y controlada por el bloque de control
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-- a la interface wishbone
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-- a la interface wishbone
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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