| Line 9... |
Line 9... |
--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This module is in the wishbone side (IEEE Std. 1284-2000).
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--| This module is in the wishbone side (IEEE Std. 1284-2000).
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | nov-2008 | First release
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--| 0.01 | nov-2008 | First release
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--| 0.1 | jan-2009 | Sinc reset
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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| Line 76... |
Line 77... |
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-- Data R/W
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-- Data R/W
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data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp)
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data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp)
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begin
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begin
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if (rst_pp = '1') then -- Reset de interfaz EPP
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data_reg <= "00000000";
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if (rst_pp = '1' or RST_I = '1') then -- Reset de interfaz EPP
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data_reg <= (others => '0');
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pre_STB_O <= '0';
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pre_STB_O <= '0';
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data_ack <= '0';
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data_ack <= '0';
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elsif (CLK_I'event and CLK_I = '1') then
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elsif (CLK_I'event and CLK_I = '1') then
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if (RST_I = '1') then -- Reset de interfaz Wishbone
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if RST_I = '1' then
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data_reg <= "00000000";
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data_reg <= (others => '0');
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pre_STB_O <= '0';
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pre_STB_O <= '0';
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data_ack <= '0';
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data_ack <= '0';
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else
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else
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if (inAutoFd = '0') then -- Data strobe
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if (inAutoFd = '0' and data_ack = '0') then -- Data strobe
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pre_STB_O <= '1';
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pre_STB_O <= '1';
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if (inStrobe = '0') then -- Escritura EPP
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if (inStrobe = '0') then -- Escritura EPP
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data_reg <= iData;
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data_reg <= iData;
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end if;
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end if;
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end if;
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end if;
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| Line 104... |
Line 106... |
end if;
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end if;
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end if;
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end if;
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if (inAutoFd = '1' and data_ack = '1') then -- iBusy solo se pondrá a cero
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if (inAutoFd = '1' and data_ack = '1') then -- iBusy solo se pondrá a cero
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data_ack <= '0'; -- una vez que haya respuesta desde la PC
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data_ack <= '0'; -- una vez que haya respuesta desde la PC
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end if;
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end if;
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end process;
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end process;
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STB_O <= pre_STB_O;
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STB_O <= pre_STB_O;
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CYC_O <= pre_STB_O;
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CYC_O <= pre_STB_O;
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DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos
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DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos
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-- a wishbone, lectura y escritura de datos desde epp
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-- a wishbone, lectura y escritura de datos desde epp
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| Line 116... |
Line 119... |
-- Adr R/W
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-- Adr R/W
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adr_ack <= not(inSelectIn); -- Autoconfirmación de estado.
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adr_ack <= not(inSelectIn); -- Autoconfirmación de estado.
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adr_strobing: process (inSelectIn, RST_I, rst_pp)
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adr_strobing: process (inSelectIn, RST_I, rst_pp)
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begin
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begin
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if (RST_I = '1' or rst_pp = '1') then
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if (RST_I = '1' or rst_pp = '1') then
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adr_reg <= "00000000";
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adr_reg <= (others => '0');
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elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
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elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
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if inStrobe = '0' then
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if inStrobe = '0' then
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adr_reg <= iData;
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adr_reg <= iData;
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end if;
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end if;
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end if;
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end if;
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| Line 129... |
Line 132... |
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-- Puerto bidireccional
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-- Puerto bidireccional
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iData <= data_reg when (inStrobe = '1' and data_ack = '1') else
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iData <= data_reg when (inStrobe = '1' and data_ack = '1') else
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adr_reg when (inStrobe = '1' and adr_ack = '1') else
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adr_reg when (inStrobe = '1' and adr_ack = '1') else
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"ZZZZZZZZ";
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(others => 'Z');
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end con_registro;
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end con_registro;
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No newline at end of file
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No newline at end of file
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