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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- UNSL
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-- UNSL - Modular Oscilloscope
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--
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--
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-- File: eppwbn_wbn_side.vhd
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-- File: eppwbn_wbn_side.vhd
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-- File history:
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-- Version: 0.20
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-- See cvs history in opencores
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-- Targeted device: Actel A3PE1500
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--
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--------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-- EPP- Wishbone bridge. This module is in the wishbone side.
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-- EPP - Wishbone bridge.
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--
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-- This module is in the wishbone side (IEEE Std. 1284-2000).
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-- Targeted device: Actel A3PR1500 <Die> <Package>
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-------------------------------------------------------------------------------
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-- Author: Facundo Aguilera
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-- File history:
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--
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-- 0.01 | nov-2008 | First release
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-- GPL
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright Facundo Aguilera 2008
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-- GPL
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-- comments in spanish
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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entity eppwbn_wbn_side is
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entity eppwbn_wbn_side is
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port(
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port(
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-- salida al puerto epp
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-- al puerto epp
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inStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 ECP/EPP (Compatibiliy)
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inStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284, Negotiation/ECP/EPP (Compatibiliy)
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-- HostClk/nWrite
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-- HostClk/nWrite
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iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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-- inAck: out std_logic; -- PtrClk/PeriphClk/Intr
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-- inAck: out std_logic; -- PtrClk/PeriphClk/Intr
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iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
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iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
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-- iPError: out std_logic; -- AckData/nAckReverse
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-- iPError: out std_logic; -- AckData/nAckReverse
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-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
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-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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inSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- iHostLogicH: in std_logic; -- (Host Logic High)
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-- iHostLogicH: in std_logic; -- (Host Logic High)
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-- i indica misma señal de salida al puerto, aunque interna en el core y controlada por el bloque de control
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-- i indica misma señal de salida al puerto, aunque interna en el core y controlada por el bloque de control
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-- salida a la interface wishbone
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-- a la interface wishbone
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_I: in std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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DAT_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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STB_O: out std_logic;
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STB_O: out std_logic;
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ACK_I: in std_logic ;
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ACK_I: in std_logic ;
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WE_O: out std_logic;
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WE_O: out std_logic;
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rst_epp: in std_logic -- reser de la interfaz EPP
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rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo
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-- selección de posición del byte
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);
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);
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end eppwbn_wbn_side;
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end eppwbn_wbn_side;
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iBusy <= adr_ack or data_ack; -- nWait. Se utiliza para confirmación de lectuira/escritura de datos/direcciones
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iBusy <= adr_ack or data_ack; -- nWait. Se utiliza para confirmación de lectuira/escritura de datos/direcciones
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WE_O <= not(inStrobe); -- Ambas señales tienen la misma utilidad, habilitan escritura
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WE_O <= not(inStrobe); -- Ambas señales tienen la misma utilidad, habilitan escritura
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-- Data R/W
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-- Data R/W
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data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_epp)
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data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp)
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begin
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begin
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if (rst_epp = '1') then -- Reset de interfaz EPP
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if (rst_pp = '1') then -- Reset de interfaz EPP
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data_reg <= "00000000";
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data_reg <= "00000000";
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pre_STB_O <= '0';
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pre_STB_O <= '0';
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data_ack <= '0';
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data_ack <= '0';
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elsif (CLK_I'event and CLK_I = '1') then
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elsif (CLK_I'event and CLK_I = '1') then
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if (RST_I = '1') then -- Reset de interfaz Wishbone
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if (RST_I = '1') then -- Reset de interfaz Wishbone
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data_reg <= DAT_I;
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data_reg <= DAT_I;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if (inAutoFd = '1' and data_ack = '1') then -- iBusy solo se pondrá a cero una vez que haya respuesta desde la PC
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if (inAutoFd = '1' and data_ack = '1') then -- iBusy solo se pondrá a cero
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data_ack <= '0';
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data_ack <= '0'; -- una vez que haya respuesta desde la PC
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end if;
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end if;
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end process;
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end process;
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STB_O <= pre_STB_O;
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STB_O <= pre_STB_O;
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CYC_O <= pre_STB_O;
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CYC_O <= pre_STB_O;
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DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos a wishbone, lectura y escritura de datos desde epp
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DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos
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-- a wishbone, lectura y escritura de datos desde epp
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-- Adr R/W
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-- Adr R/W
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adr_ack <= not(inSelectIn); -- Autoconfirmación de estado.
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adr_ack <= not(inSelectIn); -- Autoconfirmación de estado.
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adr_strobing: process (inSelectIn, RST_I, rst_epp)
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adr_strobing: process (inSelectIn, RST_I, rst_pp)
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begin
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begin
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if (RST_I = '1' or rst_epp = '1') then
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if (RST_I = '1' or rst_pp = '1') then
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adr_reg <= "00000000";
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adr_reg <= "00000000";
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elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
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elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
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if inStrobe = '0' then
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if inStrobe = '0' then
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adr_reg <= iData;
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adr_reg <= iData;
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end if;
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end if;
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