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Line 55... |
-- Known bugs :
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-- Known bugs :
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-- To Optimze :
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-- To Optimze :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- (!)
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-- (!)
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-- Original file modified to reduce code.
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-- Original file modified to reduce code and make WR and reset signals
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-- positive and make Reset sincronous
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 132... |
Line 133... |
process (clk, reset)
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process (clk, reset)
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begin -- PROCESS
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begin -- PROCESS
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-- activities triggered by asynchronous reset (active low)
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-- activities triggered by asynchronous reset (active low)
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if reset = '0' then
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-- activities triggered by rising edge of clock
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if clk'event and clk = '1' then
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if reset = '1' then
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data_out <= (others => DEFAULT_OUT);
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data_out <= (others => DEFAULT_OUT);
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init_mem ( data);
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init_mem ( data);
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else
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-- activities triggered by rising edge of clock
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elsif clk'event and clk = '1' then
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if CS = '1' then
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if CS = '1' then
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if WR = '0' then
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if WR = '1' then
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data(conv_integer(add)) <= data_in;
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data(conv_integer(add)) <= data_in;
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data_out <= (others => DEFAULT_OUT);
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data_out <= (others => DEFAULT_OUT);
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else
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else
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data_out <= data(conv_integer(add));
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data_out <= data(conv_integer(add));
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end if;
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end if;
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else
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else
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data_out <= (others => DEFAULT_OUT);
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data_out <= (others => DEFAULT_OUT);
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- end generate CS_ENABLED;
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-- end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- CS_DISABLED : if USE_CS = false generate
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-- CS_DISABLED : if USE_CS = false generate
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