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Line 56... |
-- To Optimze :
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-- To Optimze :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- (!)
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-- (!)
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-- Original file modified to reduce code and make WR and reset signals
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-- Original file modified to reduce code and make WR and reset signals
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-- positive and make Reset sincronous
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-- positive, make Reset sincronous, make data transfer asinc.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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Line 98... |
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architecture spmem_beh of mem_8bit_reset is
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architecture spmem_beh of mem_8bit_reset is
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type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
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type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
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-- signal s_reset: std_logic;
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-- Memory Type
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-- Memory Type
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signal data : data_array(0 to (2** add_width-1) ); -- Local data
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signal data : data_array(0 to (2** add_width-1) ); -- Local data
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-- FLEX/APEX devices require address to be registered with inclock for read operations
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-- FLEX/APEX devices require address to be registered with inclock for read operations
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-- This signal is used only when OPTION = 1
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-- This signal is used only when OPTION = 1
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-- signal regA : std_logic_vector( (add_width -1) downto 0);
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-- signal regA : std_logic_vector( (add_width -1) downto 0);
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procedure init_mem(signal memory_cell : inout data_array ) is
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procedure init_mem(signal memory_cell : inout data_array ) is
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Line 130... |
-- Reset_ENABLED : if USE_RESET = true generate
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-- Reset_ENABLED : if USE_RESET = true generate
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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-- CS_ENABLED : if USE_CS = true generate
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-- CS_ENABLED : if USE_CS = true generate
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process (clk, reset)
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process (clk, reset,CS,WR, add)
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begin -- PROCESS
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begin -- PROCESS
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-- activities triggered by asynchronous reset (active low)
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-- activities triggered by asynchronous reset (active low)
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-- activities triggered by rising edge of clock
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-- activities triggered by rising edge of clock
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if clk'event and clk = '1' then
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data_out <= data(conv_integer(add));
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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data_out <= (others => DEFAULT_OUT);
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init_mem ( data);
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init_mem ( data);
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else
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elsif CS = '1' then
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if CS = '1' then
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if WR = '1' then
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if WR = '1' then
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data(conv_integer(add)) <= data_in;
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data(conv_integer(add)) <= Data_In;
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data_out <= (others => DEFAULT_OUT);
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else
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data_out <= data(conv_integer(add));
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end if;
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else
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data_out <= (others => DEFAULT_OUT);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- end generate CS_ENABLED;
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-- end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- CS_DISABLED : if USE_CS = false generate
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-- CS_DISABLED : if USE_CS = false generate
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