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[/] [modular_oscilloscope/] [trunk/] [hdl/] [memory/] [dual_port_memory_wb.vhd] - Diff between revs 27 and 40

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Rev 27 Rev 40
Line 13... Line 13...
--|   
--|   
--|-------------------------------------------------------------------------------------------------
--|-------------------------------------------------------------------------------------------------
--| File history:
--| File history:
--|   0.1   | jun-2009 | First testing
--|   0.1   | jun-2009 | First testing
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--| Copyright ® 2009, Facundo Aguilera.
--| Copyright © 2009, Facundo Aguilera.
--|
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
--| modify it and/or implement it after contacting the author.
 
 
--| Wishbone Rev. B.3 compatible
--| Wishbone Rev. B.3 compatible
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
 
 
-- La memoria solo puede accederse desde la dirección 0 hasta la 15360 (11110000000000). No están 
-- La memoria solo puede accederse desde la dirección 0 hasta la 15360 (0011 11000 0000 0000). No 
-- especificados los valores obtenidos fuera de ese rango.
-- están especificados los valores obtenidos fuera de ese rango. 
 
 
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 

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