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[/] [modular_oscilloscope/] [trunk/] [hdl/] [memory/] [dual_port_memory_wb.vhd] - Diff between revs 40 and 54

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Rev 40 Rev 54
Line 12... Line 12... 
--|   with other than ProASIC3 Family FPGA.
 
--|   with other than ProASIC3 Family FPGA.
 
--|   
--|   
--|-------------------------------------------------------------------------------------------------
 
--|-------------------------------------------------------------------------------------------------
 
--| File history:
 
--| File history:
 
--|   0.1   | jun-2009 | First testing
 
--|   0.1   | jun-2009 | First testing
 
 
 
--|   0.11  | aug-2009 | Corrected error in ACK_O from port B
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
 
--| Copyright © 2009, Facundo Aguilera.
 
--| Copyright © 2009, Facundo Aguilera.
 
--|
 
--|
 
--| This VHDL design file is an open design; you can redistribute it and/or
 
--| This VHDL design file is an open design; you can redistribute it and/or
 
--| modify it and/or implement it after contacting the author.
 
--| modify it and/or implement it after contacting the author.
Line 97... Line 98... 
 
 
 
 
  -- Corrección de escritura en la misma dirección
 
  -- Corrección de escritura en la misma dirección
 
  to_BLKB <= CYC_I_b and STB_I_b and enable_BLK;
 
  to_BLKB <= CYC_I_b and STB_I_b and enable_BLK;
 
  to_BLKA <= CYC_I_a and STB_I_a;
 
  to_BLKA <= CYC_I_a and STB_I_a;
 
 
 
 
 
  enable_BLK <= '1' when ADR_I_a /= ADR_I_b and to_BLKA = '0' else
 
  enable_BLK <= '1' when ADR_I_a /= ADR_I_b or to_BLKA = '0' else
 
                '0';
 
                '0';
 
 
 
 
 
 
 
 
 
  -- Solución de ACK en puerto A
 
  -- Solución de ACK en puerto A
 
  ACK_O_a <= pre_ACK_O_a_write or pre_ACK_O_a_read;
 
  ACK_O_a <= pre_ACK_O_a_write or pre_ACK_O_a_read;

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