| Line 22... |
Line 22... |
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
|
|
|
|
-- NOTES:
|
-- NOTES:
|
-- · daq clock: 40 MHz
|
-- · daq clock: 40 MHz
|
|
-- · epp clock: 2.5 MHz
|
|
-- · (!) normal high reset button, inverted here
|
|
|
--==================================================================================================
|
--==================================================================================================
|
-- TO DO
|
-- TO DO
|
-- · Full full test
|
-- · Full full test
|
--==================================================================================================
|
--==================================================================================================
|
| Line 102... |
Line 104... |
signal ctrl_ack_i_memr: std_logic ;
|
signal ctrl_ack_i_memr: std_logic ;
|
signal ctrl_we_o_memr: std_logic;
|
signal ctrl_we_o_memr: std_logic;
|
|
|
signal clk_daq, clk_port: std_logic;
|
signal clk_daq, clk_port: std_logic;
|
|
|
|
signal inverted_reset: std_logic;
|
|
|
begin
|
begin
|
|
|
|
|
|
inverted_reset <= not(reset_I);
|
|
|
|
|
U_DAQ: daq
|
U_DAQ: daq
|
generic map(
|
generic map(
|
DEFALT_CONFIG => "0000101000000000"
|
DEFALT_CONFIG => "0000001000000000"
|
-- 5432109876543210
|
-- 5432109876543210
|
--: std_logic_vector := "0000100000000000"
|
--: std_logic_vector := "0000100000000000"
|
-- bits 8 a 0 clk_pre_scaler
|
-- bits 8 a 0 clk_pre_scaler
|
-- bits 9 clk_pre_scaler_ena
|
-- bits 9 clk_pre_scaler_ena
|
-- bit 10 adc sleep
|
-- bit 10 adc sleep
|
| Line 127... |
Line 135... |
adc_sel_O => adc_sel_O,
|
adc_sel_O => adc_sel_O,
|
adc_clk_O => adc_clk_O,
|
adc_clk_O => adc_clk_O,
|
adc_sleep_O => adc_sleep_O,
|
adc_sleep_O => adc_sleep_O,
|
adc_chip_sel_O => adc_chip_sel_O,
|
adc_chip_sel_O => adc_chip_sel_O,
|
-- Interno
|
-- Interno
|
RST_I => reset_I,
|
RST_I => inverted_reset,
|
CLK_I => clk_daq,
|
CLK_I => clk_daq,
|
DAT_I => ctrl_dat_o_daq,
|
DAT_I => ctrl_dat_o_daq,
|
ADR_I => ctrl_adr_o_daq,
|
ADR_I => ctrl_adr_o_daq,
|
CYC_I => ctrl_cyc_o_daq,
|
CYC_I => ctrl_cyc_o_daq,
|
STB_I => ctrl_stb_o_daq,
|
STB_I => ctrl_stb_o_daq,
|
| Line 158... |
Line 166... |
PeriphLogicH => PeriphLogicH_O,
|
PeriphLogicH => PeriphLogicH_O,
|
nInit => nInit_I,
|
nInit => nInit_I,
|
nFault => nFault_O,
|
nFault => nFault_O,
|
nSelectIn => nSelectIn_I,
|
nSelectIn => nSelectIn_I,
|
-- Interno
|
-- Interno
|
RST_I => reset_I,
|
RST_I => inverted_reset,
|
CLK_I => clk_port,
|
CLK_I => clk_port,
|
DAT_I => ctrl_dat_o_port,
|
DAT_I => ctrl_dat_o_port,
|
DAT_O => ctrl_dat_i_port,
|
DAT_O => ctrl_dat_i_port,
|
ADR_O => ctrl_adr_i_port,
|
ADR_O => ctrl_adr_i_port,
|
CYC_O => ctrl_cyc_i_port,
|
CYC_O => ctrl_cyc_i_port,
|
| Line 180... |
Line 188... |
CYC_I_port => ctrl_cyc_i_port,
|
CYC_I_port => ctrl_cyc_i_port,
|
STB_I_port => ctrl_stb_i_port,
|
STB_I_port => ctrl_stb_i_port,
|
ACK_O_port => ctrl_ack_o_port,
|
ACK_O_port => ctrl_ack_o_port,
|
WE_I_port => ctrl_we_i_port,
|
WE_I_port => ctrl_we_i_port,
|
CLK_I_port => clk_port,
|
CLK_I_port => clk_port,
|
RST_I_port => reset_I,
|
RST_I_port => inverted_reset,
|
|
|
DAT_I_daq => ctrl_dat_i_daq,
|
DAT_I_daq => ctrl_dat_i_daq,
|
DAT_O_daq => ctrl_dat_o_daq,
|
DAT_O_daq => ctrl_dat_o_daq,
|
ADR_O_daq => ctrl_adr_o_daq,
|
ADR_O_daq => ctrl_adr_o_daq,
|
CYC_O_daq => ctrl_cyc_o_daq,
|
CYC_O_daq => ctrl_cyc_o_daq,
|
STB_O_daq => ctrl_stb_o_daq,
|
STB_O_daq => ctrl_stb_o_daq,
|
ACK_I_daq => ctrl_ack_i_daq,
|
ACK_I_daq => ctrl_ack_i_daq,
|
WE_O_daq => ctrl_we_o_daq,
|
WE_O_daq => ctrl_we_o_daq,
|
CLK_I_daq => clk_daq,
|
CLK_I_daq => clk_daq,
|
RST_I_daq => reset_I,
|
RST_I_daq => inverted_reset,
|
|
|
DAT_O_memw => ctrl_dat_o_memw,
|
DAT_O_memw => ctrl_dat_o_memw,
|
ADR_O_memw => ctrl_adr_o_memw,
|
ADR_O_memw => ctrl_adr_o_memw,
|
CYC_O_memw => ctrl_cyc_o_memw,
|
CYC_O_memw => ctrl_cyc_o_memw,
|
STB_O_memw => ctrl_stb_o_memw,
|
STB_O_memw => ctrl_stb_o_memw,
|
| Line 210... |
Line 218... |
);
|
);
|
|
|
U_DPORTMEM: dual_port_memory_wb
|
U_DPORTMEM: dual_port_memory_wb
|
port map(
|
port map(
|
-- Puerto A (Higer prioriry)
|
-- Puerto A (Higer prioriry)
|
RST_I_a => reset_I,
|
RST_I_a => inverted_reset,
|
CLK_I_a => clk_daq,
|
CLK_I_a => clk_daq,
|
DAT_I_a => ctrl_dat_o_memw,
|
DAT_I_a => ctrl_dat_o_memw,
|
DAT_O_a => open,
|
DAT_O_a => open,
|
ADR_I_a => ctrl_adr_o_memw,
|
ADR_I_a => ctrl_adr_o_memw,
|
CYC_I_a => ctrl_cyc_o_memw,
|
CYC_I_a => ctrl_cyc_o_memw,
|
STB_I_a => ctrl_stb_o_memw,
|
STB_I_a => ctrl_stb_o_memw,
|
ACK_O_a => ctrl_ack_i_memw,
|
ACK_O_a => ctrl_ack_i_memw,
|
WE_I_a => ctrl_we_o_memw,
|
WE_I_a => ctrl_we_o_memw,
|
-- Puerto B (Lower prioriry)
|
-- Puerto B (Lower prioriry)
|
RST_I_b => reset_I,
|
RST_I_b => inverted_reset,
|
CLK_I_b => clk_port,
|
CLK_I_b => clk_port,
|
DAT_I_b => X"0000",
|
DAT_I_b => X"0000",
|
DAT_O_b => ctrl_dat_i_memr,
|
DAT_O_b => ctrl_dat_i_memr,
|
ADR_I_b => ctrl_adr_o_memr,
|
ADR_I_b => ctrl_adr_o_memr,
|
CYC_I_b => ctrl_cyc_o_memr,
|
CYC_I_b => ctrl_cyc_o_memr,
|
