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# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
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# Thu Oct 19 14:57:41 2006
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# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
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# Family: virtex2p
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# Device: xc2vp30
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# Package: ff896
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# Speed Grade: -7
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# Processor: Microblaze
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# System clock frequency: 100.000000 MHz
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# Debug interface: On-Chip HW Debug Module
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# On Chip Memory : 64 KB
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# Total Off Chip Memory : 256 MB
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# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
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# ##############################################################################
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PARAMETER VERSION = 2.1.0
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PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
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PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
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PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
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PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
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PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
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PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
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PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
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PORT sys_rst_pin = sys_rst_s, DIR = INPUT
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BEGIN microblaze
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PARAMETER INSTANCE = microblaze_0
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PARAMETER HW_VER = 4.00.a
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PARAMETER C_DEBUG_ENABLED = 1
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PARAMETER C_NUMBER_OF_PC_BRK = 2
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PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
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PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
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PARAMETER C_FSL_LINKS = 1
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BUS_INTERFACE DLMB = dlmb0
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BUS_INTERFACE ILMB = ilmb0
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BUS_INTERFACE DOPB = mb_opb
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BUS_INTERFACE IOPB = mb_opb
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BUS_INTERFACE MFSL0 = fsl0m
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BUS_INTERFACE SFSL0 = fsl0s
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PORT CLK = sys_clk_s
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PORT DBG_CAPTURE = DBG_CAPTURE_s
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PORT DBG_CLK = DBG_CLK_s
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PORT DBG_REG_EN = DBG_REG_EN_s
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PORT DBG_TDI = DBG_TDI_s
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PORT DBG_TDO = DBG_TDO_s
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PORT DBG_UPDATE = DBG_UPDATE_s
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END
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BEGIN microblaze
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PARAMETER INSTANCE = microblaze_1
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PARAMETER HW_VER = 4.00.a
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PARAMETER C_DEBUG_ENABLED = 1
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PARAMETER C_NUMBER_OF_PC_BRK = 2
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PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
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PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
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PARAMETER C_FSL_LINKS = 1
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BUS_INTERFACE DLMB = dlmb1
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BUS_INTERFACE ILMB = ilmb1
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BUS_INTERFACE DOPB = mb_opb
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BUS_INTERFACE IOPB = mb_opb
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BUS_INTERFACE SFSL0 = fsl1s
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BUS_INTERFACE MFSL0 = fsl1m
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END
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BEGIN microblaze
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PARAMETER INSTANCE = microblaze_2
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PARAMETER HW_VER = 4.00.a
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PARAMETER C_DEBUG_ENABLED = 1
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PARAMETER C_NUMBER_OF_PC_BRK = 2
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PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
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PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
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PARAMETER C_FSL_LINKS = 1
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BUS_INTERFACE DLMB = dlmb2
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BUS_INTERFACE ILMB = ilmb2
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BUS_INTERFACE DOPB = mb_opb
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BUS_INTERFACE IOPB = mb_opb
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BUS_INTERFACE SFSL0 = fsl2s
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BUS_INTERFACE MFSL0 = fsl2m
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PORT CLK = sys_clk_s
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END
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BEGIN microblaze
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PARAMETER INSTANCE = microblaze_3
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PARAMETER HW_VER = 4.00.a
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PARAMETER C_FSL_LINKS = 1
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BUS_INTERFACE DOPB = mb_opb
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BUS_INTERFACE IOPB = mb_opb
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BUS_INTERFACE DLMB = dlmb3
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BUS_INTERFACE ILMB = ilmb3
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BUS_INTERFACE SFSL0 = fsl3s
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BUS_INTERFACE MFSL0 = fsl3m
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END
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BEGIN opb_v20
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PARAMETER INSTANCE = mb_opb
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PARAMETER HW_VER = 1.10.c
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT OPB_Clk = sys_clk_s
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END
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BEGIN opb_mdm
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PARAMETER INSTANCE = debug_module
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_MB_DBG_PORTS = 1
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PARAMETER C_USE_UART = 1
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PARAMETER C_UART_WIDTH = 8
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PARAMETER C_BASEADDR = 0x41400000
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PARAMETER C_HIGHADDR = 0x4140ffff
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BUS_INTERFACE SOPB = mb_opb
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PORT OPB_Clk = sys_clk_s
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PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
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PORT DBG_CLK_0 = DBG_CLK_s
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PORT DBG_REG_EN_0 = DBG_REG_EN_s
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PORT DBG_TDI_0 = DBG_TDI_s
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PORT DBG_TDO_0 = DBG_TDO_s
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PORT DBG_UPDATE_0 = DBG_UPDATE_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = ilmb0
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = dlmb0
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = ilmb1
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = dlmb1
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = ilmb2
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = dlmb2
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = ilmb3
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = dlmb3
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT SYS_Rst = sys_rst_s
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PORT LMB_Clk = sys_clk_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl0m
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl0s
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl1m
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl1s
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl2m
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl2s
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl3m
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN fsl_v20
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PARAMETER INSTANCE = fsl3s
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_FSL_DEPTH = 128
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PORT FSL_Clk = sys_clk_s
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PORT SYS_Rst = sys_rst_s
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = dlmb_cntlr0
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x0000ffff
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BUS_INTERFACE SLMB = dlmb0
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BUS_INTERFACE BRAM_PORT = dlmb_port0
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = ilmb_cntlr0
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x0000ffff
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BUS_INTERFACE SLMB = ilmb0
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BUS_INTERFACE BRAM_PORT = ilmb_port0
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END
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BEGIN bram_block
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PARAMETER INSTANCE = lmb_bram0
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = ilmb_port0
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BUS_INTERFACE PORTB = dlmb_port0
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = dlmb_cntlr1
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE SLMB = dlmb1
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BUS_INTERFACE BRAM_PORT = dmb_port1
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = ilmb_cntlr1
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE SLMB = ilmb1
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BUS_INTERFACE BRAM_PORT = ilmb_port1
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END
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BEGIN bram_block
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PARAMETER INSTANCE = lmb_bram1
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = ilmb_port1
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BUS_INTERFACE PORTB = dmb_port1
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = dlmb_cntlr2
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE SLMB = dlmb2
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BUS_INTERFACE BRAM_PORT = dlmb_port2
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = ilmb_cntlr2
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE SLMB = ilmb2
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BUS_INTERFACE BRAM_PORT = ilmb_port2
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END
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BEGIN bram_block
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PARAMETER INSTANCE = lmb_bram2
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = ilmb_port2
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BUS_INTERFACE PORTB = dlmb_port2
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = dlmb_cntlr3
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE BRAM_PORT = dlmb_port3
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BUS_INTERFACE SLMB = dlmb3
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = ilmb_cntlr3
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE BRAM_PORT = ilmb_port3
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BUS_INTERFACE SLMB = ilmb3
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END
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BEGIN bram_block
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PARAMETER INSTANCE = lmb_bram3
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = ilmb_port3
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BUS_INTERFACE PORTB = dlmb_port3
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END
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BEGIN opb_uartlite
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PARAMETER INSTANCE = RS232_Uart_1
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BAUDRATE = 9600
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_ODD_PARITY = 0
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_CLK_FREQ = 100000000
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PARAMETER C_BASEADDR = 0x40600000
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PARAMETER C_HIGHADDR = 0x4060ffff
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BUS_INTERFACE SOPB = mb_opb
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PORT OPB_Clk = sys_clk_s
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PORT RX = fpga_0_RS232_Uart_1_RX
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PORT TX = fpga_0_RS232_Uart_1_TX
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END
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BEGIN opb_sysace
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PARAMETER INSTANCE = SysACE_CompactFlash
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PARAMETER HW_VER = 1.00.c
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PARAMETER C_MEM_WIDTH = 16
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PARAMETER C_BASEADDR = 0x41800000
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PARAMETER C_HIGHADDR = 0x4180ffff
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BUS_INTERFACE SOPB = mb_opb
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PORT OPB_Clk = sys_clk_s
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PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
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PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
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PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
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PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
|
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PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
|
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PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
|
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PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
|
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END
|
|
|
|
BEGIN opb_ddr
|
|
PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
|
|
PARAMETER HW_VER = 2.00.b
|
|
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
|
|
PARAMETER C_NUM_BANKS_MEM = 1
|
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PARAMETER C_NUM_CLK_PAIRS = 4
|
|
PARAMETER C_REG_DIMM = 0
|
|
PARAMETER C_DDR_TMRD = 20000
|
|
PARAMETER C_DDR_TWR = 20000
|
|
PARAMETER C_DDR_TRAS = 60000
|
|
PARAMETER C_DDR_TRC = 90000
|
|
PARAMETER C_DDR_TRFC = 100000
|
|
PARAMETER C_DDR_TRCD = 30000
|
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PARAMETER C_DDR_TRRD = 20000
|
|
PARAMETER C_DDR_TRP = 30000
|
|
PARAMETER C_DDR_TREFC = 70300000
|
|
PARAMETER C_DDR_AWIDTH = 13
|
|
PARAMETER C_DDR_COL_AWIDTH = 10
|
|
PARAMETER C_DDR_BANK_AWIDTH = 2
|
|
PARAMETER C_DDR_DWIDTH = 64
|
|
PARAMETER C_MEM0_BASEADDR = 0x30000000
|
|
PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
|
|
BUS_INTERFACE SOPB = mb_opb
|
|
PORT OPB_Clk = sys_clk_s
|
|
PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
|
|
PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
|
|
PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
|
|
PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
|
|
PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
|
|
PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
|
|
PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
|
|
PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
|
|
PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
|
|
PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
|
|
PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
|
|
PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
|
|
PORT Device_Clk90_in = clk_90_s
|
|
PORT Device_Clk90_in_n = clk_90_n_s
|
|
PORT Device_Clk = sys_clk_s
|
|
PORT Device_Clk_n = sys_clk_n_s
|
|
PORT DDR_Clk90_in = ddr_clk_90_s
|
|
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
|
|
END
|
|
|
|
BEGIN util_vector_logic
|
|
PARAMETER INSTANCE = sysclk_inv
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_SIZE = 1
|
|
PARAMETER C_OPERATION = not
|
|
PORT Op1 = sys_clk_s
|
|
PORT Res = sys_clk_n_s
|
|
END
|
|
|
|
BEGIN util_vector_logic
|
|
PARAMETER INSTANCE = clk90_inv
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_SIZE = 1
|
|
PARAMETER C_OPERATION = not
|
|
PORT Op1 = clk_90_s
|
|
PORT Res = clk_90_n_s
|
|
END
|
|
|
|
BEGIN util_vector_logic
|
|
PARAMETER INSTANCE = ddr_clk90_inv
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_SIZE = 1
|
|
PARAMETER C_OPERATION = not
|
|
PORT Op1 = ddr_clk_90_s
|
|
PORT Res = ddr_clk_90_n_s
|
|
END
|
|
|
|
BEGIN dcm_module
|
|
PARAMETER INSTANCE = dcm_0
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_CLK0_BUF = TRUE
|
|
PARAMETER C_CLK90_BUF = TRUE
|
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
|
PARAMETER C_CLK_FEEDBACK = 1X
|
|
PARAMETER C_EXT_RESET_HIGH = 1
|
|
PORT CLKIN = dcm_clk_s
|
|
PORT CLK0 = sys_clk_s
|
|
PORT CLK90 = clk_90_s
|
|
PORT CLKFB = sys_clk_s
|
|
PORT RST = net_gnd
|
|
PORT LOCKED = dcm_0_lock
|
|
END
|
|
|
|
BEGIN dcm_module
|
|
PARAMETER INSTANCE = dcm_1
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_CLK0_BUF = TRUE
|
|
PARAMETER C_CLK90_BUF = TRUE
|
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
|
PARAMETER C_CLK_FEEDBACK = 1X
|
|
PARAMETER C_PHASE_SHIFT = 60
|
|
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
|
|
PARAMETER C_EXT_RESET_HIGH = 0
|
|
PORT CLKIN = ddr_feedback_s
|
|
PORT CLK90 = ddr_clk_90_s
|
|
PORT CLK0 = dcm_1_FB
|
|
PORT CLKFB = dcm_1_FB
|
|
PORT RST = dcm_0_lock
|
|
PORT LOCKED = dcm_1_lock
|
|
END
|
|
|
|
BEGIN fifo_link
|
|
PARAMETER INSTANCE = fifo01
|
|
PARAMETER HW_VER = 1.00.a
|
|
BUS_INTERFACE SFSL = fsl0m
|
|
BUS_INTERFACE MFSL = fsl1s
|
|
END
|
|
|
|
BEGIN fifo_link
|
|
PARAMETER INSTANCE = fifo12
|
|
PARAMETER HW_VER = 1.00.a
|
|
BUS_INTERFACE SFSL = fsl1m
|
|
BUS_INTERFACE MFSL = fsl2s
|
|
END
|
|
|
|
BEGIN fifo_link
|
|
PARAMETER INSTANCE = fifo23
|
|
PARAMETER HW_VER = 1.00.a
|
|
BUS_INTERFACE SFSL = fsl2m
|
|
BUS_INTERFACE MFSL = fsl3s
|
|
END
|
|
|
|
BEGIN fifo_link
|
|
PARAMETER INSTANCE = fifo30
|
|
PARAMETER HW_VER = 1.00.a
|
|
BUS_INTERFACE SFSL = fsl3m
|
|
BUS_INTERFACE MFSL = fsl0s
|
|
END
|
|
|
