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# MPMC8 - Multiport Memory Controller
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# MPMC9 - Multiport Memory Controller
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## Overview
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## Overview
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The multi-port memory controller provides eight access ports with either small streaming read caches or a 16kB shared read cache to the ddr3 ram. The multi-port memory controller interfaces between the SoC and a MIG controller.
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The multi-port memory controller provides eight access ports with either small streaming read caches or a 16kB shared read cache to the ddr3 ram. The multi-port memory controller interfaces between the SoC and a MIG controller.
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Ports may be customized with parameter settings. Port #5 is setup to handle sprites and is read-only.
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Ports may be customized with parameter settings. Port #5 is setup to handle sprites and is read-only.
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# Read Cache / Streaming Cache
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# Read Cache / Streaming Cache
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The read cache is a 16kB direct mapped cache which may be shared between ports. The cache line size is 16 bytes. Note the cache only caches read operations. Writes cause the corresponding cache line to be invalidated to maintain cache coherency. Writes bypass the cache and write directly to memory.
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The read cache is a 16kB direct mapped cache which may be shared between ports. The cache line size is 16 bytes. Note the cache only caches read operations. Writes cause the corresponding cache line to be invalidated to maintain cache coherency. Writes bypass the cache and write directly to memory.
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## Address Reservations
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## Address Reservations
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The controller supports address reservations on memory for imnplementation of semaphores. The CPU must output address reservation set and clear signals to support this.
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The controller supports address reservations on memory for imnplementation of semaphores. The CPU must output address reservation set and clear signals to support this.
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## Parameters
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## Parameters
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STREAMn - cause port number 'n' to use a streaming cache instead of the main cache
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STREAMn - cause port number 'n' to use a streaming cache instead of the main cache
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STRIPSn - sets the number of memory strips (16 byte accesses) minus 1 for port 'n' to load consecutively (should be 0 (for 1), 1, 3, or 7 (for 8))
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STRIPSn - sets the number of memory strips (16 byte accesses) minus 1 for port 'n' to load consecutively (should be 0 (for 1), 1, 3, 7 (for 8), 63)
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CnW - sets the data width for the port (Note port #7 C7R must also be set)
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CnW - sets the data width for the port (Note port #7 C7R must also be set)
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NAR - sets the number of outstanding address reservation that are present, this should be a small number (eg. 2)
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NAR - sets the number of outstanding address reservation that are present, this should be a small number (eg. 2)
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