A new version of the core, MPMC10, is in the works. The new version will feature better performance through the use of a input fifo. It is much the same as MPMC9. All ports are 128 bit. Testing with video circuits reveals MPMC10 still has some glitches to work out. Port priorities are now round-robin.
# MPMC9 - Multiport Memory Controller
# MPMC9 - Multiport Memory Controller
## Overview
## Overview
The multi-port memory controller provides eight access ports with either small streaming read caches or a 16kB shared read cache to the ddr3 ram. The multi-port memory controller interfaces between the SoC and a MIG controller.
The multi-port memory controller provides eight access ports with either small streaming read caches or a 16kB shared read cache to the ddr3 ram. The multi-port memory controller interfaces between the SoC and a MIG controller.
Ports may be customized with parameter settings. Port #5 is setup to handle sprites and is read-only.
Ports may be customized with parameter settings. Port #5 is setup to handle sprites and is read-only.
