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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2015-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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| Line 37... |
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import const_pkg::*;
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import const_pkg::*;
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import wishbone_pkg::*;
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import wishbone_pkg::*;
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import mpmc10_pkg::*;
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import mpmc10_pkg::*;
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module mpmc10_cache_wb (input rst, wclk, inv,
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module mpmc10_cache_wb (input rst, wclk, inv,
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input wb_write_request128_t wchi,
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input wb_cmd_request128_t wchi,
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output wb_write_response_t wcho,
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output wb_write_response_t wcho,
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input wb_write_request128_t ld,
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input wb_cmd_request128_t ld,
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input ch0clk,
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input ch0clk,
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input ch1clk,
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input ch1clk,
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input ch2clk,
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input ch2clk,
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input ch3clk,
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input ch3clk,
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input ch4clk,
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input ch4clk,
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input ch5clk,
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input ch5clk,
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input ch6clk,
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input ch6clk,
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input ch7clk,
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input ch7clk,
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input wb_write_request128_t ch0i,
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input wb_cmd_request128_t ch0i,
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input wb_write_request128_t ch1i,
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input wb_cmd_request128_t ch1i,
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input wb_write_request128_t ch2i,
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input wb_cmd_request128_t ch2i,
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input wb_write_request128_t ch3i,
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input wb_cmd_request128_t ch3i,
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input wb_write_request128_t ch4i,
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input wb_cmd_request128_t ch4i,
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input wb_write_request128_t ch5i,
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input wb_cmd_request128_t ch5i,
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input wb_write_request128_t ch6i,
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input wb_cmd_request128_t ch6i,
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input wb_write_request128_t ch7i,
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input wb_cmd_request128_t ch7i,
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input ch0wack,
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input ch0wack,
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input ch1wack,
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input ch1wack,
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input ch2wack,
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input ch2wack,
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input ch3wack,
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input ch3wack,
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input ch4wack,
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input ch4wack,
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input ch5wack,
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input ch5wack,
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input ch6wack,
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input ch6wack,
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input ch7wack,
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input ch7wack,
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output wb_read_response128_t ch0o,
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output wb_cmd_response128_t ch0o,
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output wb_read_response128_t ch1o,
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output wb_cmd_response128_t ch1o,
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output wb_read_response128_t ch2o,
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output wb_cmd_response128_t ch2o,
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output wb_read_response128_t ch3o,
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output wb_cmd_response128_t ch3o,
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output wb_read_response128_t ch4o,
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output wb_cmd_response128_t ch4o,
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output wb_read_response128_t ch5o,
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output wb_cmd_response128_t ch5o,
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output wb_read_response128_t ch6o,
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output wb_cmd_response128_t ch6o,
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output wb_read_response128_t ch7o
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output wb_cmd_response128_t ch7o,
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output reg ch0hit,
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output reg ch1hit,
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output reg ch2hit,
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output reg ch3hit,
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output reg ch4hit,
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output reg ch5hit,
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output reg ch6hit,
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output reg ch7hit
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);
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);
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parameter DEP=1024;
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parameter DEP=1024;
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parameter LOBIT=4;
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parameter LOBIT=4;
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parameter HIBIT=13;
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parameter HIBIT=13;
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Line 139... |
reg stb5;
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reg stb5;
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reg stb6;
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reg stb6;
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reg stb7;
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reg stb7;
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reg [8:0] rstb;
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reg [8:0] rstb;
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always_ff @(posedge ch0clk) radrr[0] <= ch0i.adr;
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always_ff @(posedge ch0clk) radrr[0] <= ch0i.padr;
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always_ff @(posedge ch1clk) radrr[1] <= ch1i.adr;
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always_ff @(posedge ch1clk) radrr[1] <= ch1i.padr;
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always_ff @(posedge ch2clk) radrr[2] <= ch2i.adr;
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always_ff @(posedge ch2clk) radrr[2] <= ch2i.padr;
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always_ff @(posedge ch3clk) radrr[3] <= ch3i.adr;
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always_ff @(posedge ch3clk) radrr[3] <= ch3i.padr;
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always_ff @(posedge ch4clk) radrr[4] <= ch4i.adr;
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always_ff @(posedge ch4clk) radrr[4] <= ch4i.padr;
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always_ff @(posedge ch5clk) radrr[5] <= ch5i.adr;
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always_ff @(posedge ch5clk) radrr[5] <= ch5i.padr;
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always_ff @(posedge ch6clk) radrr[6] <= ch6i.adr;
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always_ff @(posedge ch6clk) radrr[6] <= ch6i.padr;
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always_ff @(posedge ch7clk) radrr[7] <= ch7i.adr;
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always_ff @(posedge ch7clk) radrr[7] <= ch7i.padr;
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always_ff @(posedge wclk) radrr[8] <= ld.cyc ? ld.adr : wchi.adr;
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always_ff @(posedge wclk) radrr[8] <= ld.cyc ? ld.padr : wchi.padr;
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always_ff @(posedge wclk) wchi_adr1 <= wchi.adr;
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always_ff @(posedge wclk) wchi_adr1 <= wchi.padr;
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always_ff @(posedge wclk) wchi_adr <= wchi_adr1;
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always_ff @(posedge wclk) wchi_adr <= wchi_adr1;
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always_ff @(posedge ch0clk) stb0 <= ch0i.stb;
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always_ff @(posedge ch0clk) stb0 <= ch0i.stb;
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always_ff @(posedge ch1clk) stb1 <= ch1i.stb;
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always_ff @(posedge ch1clk) stb1 <= ch1i.stb;
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always_ff @(posedge ch2clk) stb2 <= ch2i.stb;
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always_ff @(posedge ch2clk) stb2 <= ch2i.stb;
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Line 173... |
always_comb rstb[8] <= ld.cyc ? ld.stb : wchi.stb;
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always_comb rstb[8] <= ld.cyc ? ld.stb : wchi.stb;
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always_ff @(posedge wclk) wchi_stb_r <= wchi.stb;
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always_ff @(posedge wclk) wchi_stb_r <= wchi.stb;
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always_ff @(posedge wclk) wchi_stb <= wchi_stb_r;
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always_ff @(posedge wclk) wchi_stb <= wchi_stb_r;
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always_ff @(posedge wclk) wchi_sel <= wchi.sel;
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always_ff @(posedge wclk) wchi_sel <= wchi.sel;
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always_ff @(posedge wclk) wchi_dat <= wchi.dat;
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always_ff @(posedge wclk) wchi_dat <= wchi.data1;
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reg [8:0] rclkp;
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reg [8:0] rclkp;
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always_comb
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always_comb
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begin
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begin
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rclkp[0] = ch0clk;
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rclkp[0] = ch0clk;
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Line 192... |
end
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end
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reg [HIBIT-LOBIT:0] radr [0:8];
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reg [HIBIT-LOBIT:0] radr [0:8];
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always_comb
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always_comb
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begin
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begin
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radr[0] = ch0i.adr[HIBIT:LOBIT];
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radr[0] = ch0i.padr[HIBIT:LOBIT];
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radr[1] = ch1i.adr[HIBIT:LOBIT];
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radr[1] = ch1i.padr[HIBIT:LOBIT];
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radr[2] = ch2i.adr[HIBIT:LOBIT];
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radr[2] = ch2i.padr[HIBIT:LOBIT];
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radr[3] = ch3i.adr[HIBIT:LOBIT];
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radr[3] = ch3i.padr[HIBIT:LOBIT];
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radr[4] = ch4i.adr[HIBIT:LOBIT];
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radr[4] = ch4i.padr[HIBIT:LOBIT];
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radr[5] = ch5i.adr[HIBIT:LOBIT];
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radr[5] = ch5i.padr[HIBIT:LOBIT];
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radr[6] = ch6i.adr[HIBIT:LOBIT];
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radr[6] = ch6i.padr[HIBIT:LOBIT];
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radr[7] = ch7i.adr[HIBIT:LOBIT];
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radr[7] = ch7i.padr[HIBIT:LOBIT];
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radr[8] = ld.cyc ? ld.adr[HIBIT:LOBIT] : wchi.adr[HIBIT:LOBIT];
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radr[8] = ld.cyc ? ld.padr[HIBIT:LOBIT] : wchi.padr[HIBIT:LOBIT];
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end
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end
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// xpm_memory_sdpram: Simple Dual Port RAM
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// xpm_memory_sdpram: Simple Dual Port RAM
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// Xilinx Parameterized Macro, version 2020.2
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// Xilinx Parameterized Macro, version 2020.2
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Line 311... |
always_ff @(posedge ch5clk) hit5a[g] = (doutb[5].lines[g].tag==radrr[5][31:LOBIT]) && (vbito5a[g]==1'b1);
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always_ff @(posedge ch5clk) hit5a[g] = (doutb[5].lines[g].tag==radrr[5][31:LOBIT]) && (vbito5a[g]==1'b1);
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always_ff @(posedge ch6clk) hit6a[g] = (doutb[6].lines[g].tag==radrr[6][31:LOBIT]) && (vbito6a[g]==1'b1);
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always_ff @(posedge ch6clk) hit6a[g] = (doutb[6].lines[g].tag==radrr[6][31:LOBIT]) && (vbito6a[g]==1'b1);
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always_ff @(posedge ch7clk) hit7a[g] = (doutb[7].lines[g].tag==radrr[7][31:LOBIT]) && (vbito7a[g]==1'b1);
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always_ff @(posedge ch7clk) hit7a[g] = (doutb[7].lines[g].tag==radrr[7][31:LOBIT]) && (vbito7a[g]==1'b1);
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always_ff @(posedge wclk) hit8a[g] = (doutb[8].lines[g].tag==radrr[8][31:LOBIT]) && (vbito8a[g]==1'b1);
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always_ff @(posedge wclk) hit8a[g] = (doutb[8].lines[g].tag==radrr[8][31:LOBIT]) && (vbito8a[g]==1'b1);
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end
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end
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always_comb ch0o.ack = (|hit0a & stb0) | (ch0wack & stb0);
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always_comb ch0hit = |hit0a & stb0;
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always_comb ch1o.ack = (|hit1a & stb1) | (ch1wack & stb1);
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always_comb ch1hit = |hit1a & stb1;
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always_comb ch2o.ack = (|hit2a & stb2) | (ch2wack & stb2);
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always_comb ch2hit = |hit2a & stb2;
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always_comb ch3o.ack = (|hit3a & stb3) | (ch3wack & stb3);
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always_comb ch3hit = |hit3a & stb3;
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always_comb ch4o.ack = (|hit4a & stb4) | (ch4wack & stb4);
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always_comb ch4hit = |hit4a & stb4;
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always_comb ch5o.ack = (|hit5a & stb5) | (ch5wack & stb5);
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always_comb ch5hit = |hit5a & stb5;
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always_comb ch6o.ack = (|hit6a & stb6) | (ch6wack & stb6);
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always_comb ch6hit = |hit6a & stb6;
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always_comb ch7o.ack = (|hit7a & stb7) | (ch7wack & stb7);
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always_comb ch7hit = |hit7a & stb7;
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always_comb ch0o.ack = (|hit0a && stb0 && (ch0i.cmd==CMD_LOAD||ch0i.cmd==CMD_LOADZ)) | (ch0wack & stb0);
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always_comb ch1o.ack = (|hit1a && stb1 && (ch1i.cmd==CMD_LOAD||ch1i.cmd==CMD_LOADZ)) | (ch1wack & stb1);
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always_comb ch2o.ack = (|hit2a && stb2 && (ch2i.cmd==CMD_LOAD||ch2i.cmd==CMD_LOADZ)) | (ch2wack & stb2);
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always_comb ch3o.ack = (|hit3a && stb3 && (ch3i.cmd==CMD_LOAD||ch3i.cmd==CMD_LOADZ)) | (ch3wack & stb3);
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always_comb ch4o.ack = (|hit4a && stb4 && (ch4i.cmd==CMD_LOAD||ch4i.cmd==CMD_LOADZ)) | (ch4wack & stb4);
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always_comb ch5o.ack = (|hit5a && stb5 && (ch5i.cmd==CMD_LOAD||ch5i.cmd==CMD_LOADZ)) | (ch5wack & stb5);
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always_comb ch6o.ack = (|hit6a && stb6 && (ch6i.cmd==CMD_LOAD||ch6i.cmd==CMD_LOADZ)) | (ch6wack & stb6);
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always_comb ch7o.ack = (|hit7a && stb7 && (ch7i.cmd==CMD_LOAD||ch7i.cmd==CMD_LOADZ)) | (ch7wack & stb7);
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always_comb ch0o.err = 1'b0;
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always_comb ch0o.err = 1'b0;
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always_comb ch1o.err = 1'b0;
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always_comb ch1o.err = 1'b0;
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always_comb ch2o.err = 1'b0;
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always_comb ch2o.err = 1'b0;
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always_comb ch3o.err = 1'b0;
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always_comb ch3o.err = 1'b0;
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always_comb ch4o.err = 1'b0;
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always_comb ch4o.err = 1'b0;
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Line 351... |
always_comb ch3o.cid = ch3i.cid;
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always_comb ch3o.cid = ch3i.cid;
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always_comb ch4o.cid = ch4i.cid;
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always_comb ch4o.cid = ch4i.cid;
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always_comb ch5o.cid = ch5i.cid;
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always_comb ch5o.cid = ch5i.cid;
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always_comb ch6o.cid = ch6i.cid;
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always_comb ch6o.cid = ch6i.cid;
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always_comb ch7o.cid = ch7i.cid;
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always_comb ch7o.cid = ch7i.cid;
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always_comb ch0o.tid = ch0i.tid;
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always_comb ch1o.tid = ch1i.tid;
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always_comb ch2o.tid = ch2i.tid;
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always_comb ch3o.tid = ch3i.tid;
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always_comb ch4o.tid = ch4i.tid;
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always_comb ch5o.tid = ch5i.tid;
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always_comb ch6o.tid = ch6i.tid;
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always_comb ch7o.tid = ch7i.tid;
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end
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end
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endgenerate
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endgenerate
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always_comb wway = hit8a[0] ? 2'd0 : hit8a[1] ? 2'd1 : hit8a[2] ? 2'd2 : hit8a[3] ? 2'd3 : 2'd0;
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always_comb wway = hit8a[0] ? 2'd0 : hit8a[1] ? 2'd1 : hit8a[2] ? 2'd2 : hit8a[3] ? 2'd3 : 2'd0;
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Line 425... |
// due to a read miss. For a read miss the entire line is updated, otherwise
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// due to a read miss. For a read miss the entire line is updated, otherwise
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// just the part of the line relevant to the write is updated.
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// just the part of the line relevant to the write is updated.
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always_ff @(posedge wclk)
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always_ff @(posedge wclk)
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begin
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begin
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if (ld.cyc)
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if (ld.cyc)
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wadr <= ld.adr;
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wadr <= ld.padr;
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else if (wchi.stb)
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else if (wchi.stb)
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wadr <= wchi.adr;
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wadr <= wchi.padr;
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end
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end
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always_ff @(posedge wclk)
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always_ff @(posedge wclk)
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wadr2 <= wadr;
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wadr2 <= wadr;
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always_ff @(posedge wclk)
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always_ff @(posedge wclk)
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lddat1 <= ld.dat;
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lddat1 <= ld.data1;
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always_ff @(posedge wclk)
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always_ff @(posedge wclk)
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lddat2 <= lddat1;
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lddat2 <= lddat1;
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always_ff @(posedge wclk)
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always_ff @(posedge wclk)
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wstrb <= ldcycd2 | (wchi_stb & |hit8a & wchi.we);
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wstrb <= ldcycd2 | (wchi_stb & |hit8a & wchi.we);
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