| Line 88... |
Line 88... |
vbit[n5] <= 'd0;
|
vbit[n5] <= 'd0;
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end
|
end
|
|
|
reg [31:0] radrr [0:8];
|
reg [31:0] radrr [0:8];
|
reg wchi_stb, wchi_stb_r;
|
reg wchi_stb, wchi_stb_r;
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reg [15:0] wchi_sel, wchi_sel_r;
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reg [15:0] wchi_sel;
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reg [31:0] wchi_adr, wchi_adr1;
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reg [31:0] wchi_adr, wchi_adr1;
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reg [127:0] wchi_dat;
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reg [127:0] wchi_dat;
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|
|
mpmc10_quad_cache_line_t doutb [0:8];
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mpmc10_quad_cache_line_t doutb [0:8];
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mpmc10_quad_cache_line_t wrdata, wdata;
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mpmc10_quad_cache_line_t wrdata, wdata;
|
| Line 164... |
Line 164... |
always_comb rstb[7] <= ch7i.stb & ~ch7i.we;
|
always_comb rstb[7] <= ch7i.stb & ~ch7i.we;
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always_comb rstb[8] <= ld.cyc ? ld.stb : wchi.stb;
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always_comb rstb[8] <= ld.cyc ? ld.stb : wchi.stb;
|
|
|
always_ff @(posedge wclk) wchi_stb_r <= wchi.stb;
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always_ff @(posedge wclk) wchi_stb_r <= wchi.stb;
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always_ff @(posedge wclk) wchi_stb <= wchi_stb_r;
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always_ff @(posedge wclk) wchi_stb <= wchi_stb_r;
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always_ff @(posedge wclk) wchi_sel_r <= wchi.sel;
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always_ff @(posedge wclk) wchi_sel <= wchi.sel;
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always_ff @(posedge wclk) wchi_sel <= wchi_sel_r;
|
|
always_ff @(posedge wclk) wchi_dat <= wchi.dat;
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always_ff @(posedge wclk) wchi_dat <= wchi.dat;
|
|
|
reg [8:0] rclkp;
|
reg [8:0] rclkp;
|
always_comb
|
always_comb
|
begin
|
begin
|
| Line 402... |
Line 401... |
// just the part of the line relevant to the write is updated.
|
// just the part of the line relevant to the write is updated.
|
always_ff @(posedge wclk)
|
always_ff @(posedge wclk)
|
begin
|
begin
|
if (ld.cyc)
|
if (ld.cyc)
|
wadr <= ld.adr;
|
wadr <= ld.adr;
|
else if (wchi_stb)
|
else if (wchi.stb)
|
wadr <= wchi_adr;
|
wadr <= wchi.adr;
|
wstrb <= ldcycd2 | (wchi_stb & |hit8a & wchi.we);
|
|
end
|
end
|
always_ff @(posedge wclk)
|
always_ff @(posedge wclk)
|
wadr2 <= wadr;
|
wadr2 <= wadr;
|
always_ff @(posedge wclk)
|
always_ff @(posedge wclk)
|
lddat1 <= ld.dat;
|
lddat1 <= ld.dat;
|
always_ff @(posedge wclk)
|
always_ff @(posedge wclk)
|
lddat2 <= lddat1;
|
lddat2 <= lddat1;
|
|
always_ff @(posedge wclk)
|
|
wstrb <= ldcycd2 | (wchi_stb & |hit8a & wchi.we);
|
|
|
// Merge write data into cache line.
|
// Merge write data into cache line.
|
// For a load due to a read miss the entire line is updated.
|
// For a load due to a read miss the entire line is updated.
|
// For a write hit, just the portion of the line corresponding to the hit is
|
// For a write hit, just the portion of the line corresponding to the hit is
|
// updated.
|
// updated.
|
