URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

Subversion Repositories mpmc8

[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_data_select.sv] - Diff between revs 7 and 11

Rev 7	Rev 11
Line 1...	Line 1...
`timescale 1ns / 1ps	`timescale 1ns / 1ps
`// ============================================================================`	`// ============================================================================`
`// __`	`// __`
`// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo`	`// \\__/ o\ (C) 2015-2023 Robert Finch, Waterloo`
`// \ __ / All rights reserved.`	`// \ __ / All rights reserved.`
`// \/_// robfinch@finitron.ca`	`// \/_// robfinch@finitron.ca`
`// \|\|`	`// \|\|`
`//`	`//`
`// BSD 3-Clause License`	`// BSD 3-Clause License`
Line 34...	Line 34...
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
`import mpmc10_pkg::*;`	`import mpmc10_pkg::*;`

`module mpmc10_data_select(clk, state, dati, dato);`	`module mpmc10_data_select(clk, state, dati1, dati2, dato1, dato2);`
`parameter WID=256;`	`parameter WID=256;`
`input clk;`	`input clk;`
`input mpmc10_state_t state;`	`input mpmc10_state_t state;`
`input [WID-1:0] dati;`	`input [WID-1:0] dati1;`
`output reg [WID-1:0] dato;`	`input [WID-1:0] dati2;`
	`output reg [WID-1:0] dato1;`
	`output reg [WID-1:0] dato2;`

`// Setting the write data`	`// Setting the write data`
`always_ff @(posedge clk)`	`always_ff @(posedge clk)`
`if (state==PRESET2) begin`	`if (state==PRESET2) begin`
`dato <= dati;`	`dato1 <= dati1;`
	`dato2 <= dati2;`
`end`	`end`

`endmodule`	`endmodule`