| Line 40... |
Line 40... |
full, empty, almost_full, rd_rst_busy, wr_rst_busy, cnt);
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full, empty, almost_full, rd_rst_busy, wr_rst_busy, cnt);
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input rst;
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input rst;
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input clk;
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input clk;
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input rd_fifo;
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input rd_fifo;
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input wr_fifo;
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input wr_fifo;
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input wb_write_request128_t req_fifoi;
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input wb_cmd_request128_t req_fifoi;
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output wb_write_request128_t req_fifoo;
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output wb_cmd_request128_t req_fifoo;
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output v;
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output v;
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output full;
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output full;
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output empty;
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output empty;
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output almost_full;
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output almost_full;
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output rd_rst_busy;
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output rd_rst_busy;
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| Line 60... |
Line 60... |
.FIFO_WRITE_DEPTH(32), // DECIMAL
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.FIFO_WRITE_DEPTH(32), // DECIMAL
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.FULL_RESET_VALUE(0), // DECIMAL
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.FULL_RESET_VALUE(0), // DECIMAL
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.PROG_EMPTY_THRESH(3), // DECIMAL
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.PROG_EMPTY_THRESH(3), // DECIMAL
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.PROG_FULL_THRESH(27), // DECIMAL
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.PROG_FULL_THRESH(27), // DECIMAL
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.RD_DATA_COUNT_WIDTH(5), // DECIMAL
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.RD_DATA_COUNT_WIDTH(5), // DECIMAL
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.READ_DATA_WIDTH($bits(wb_write_request128_t)), // DECIMAL
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.READ_DATA_WIDTH($bits(wb_cmd_request128_t)), // DECIMAL
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.READ_MODE("std"), // String
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.READ_MODE("std"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_ADV_FEATURES("070F"), // String
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.USE_ADV_FEATURES("070F"), // String
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.WAKEUP_TIME(0), // DECIMAL
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.WAKEUP_TIME(0), // DECIMAL
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.WRITE_DATA_WIDTH($bits(wb_write_request128_t)), // DECIMAL
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.WRITE_DATA_WIDTH($bits(wb_cmd_request128_t)), // DECIMAL
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.WR_DATA_COUNT_WIDTH(5) // DECIMAL
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.WR_DATA_COUNT_WIDTH(5) // DECIMAL
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)
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)
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xpm_fifo_sync_inst (
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xpm_fifo_sync_inst (
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.almost_empty(), // 1-bit output: Almost Empty : When asserted, this signal indicates that
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.almost_empty(), // 1-bit output: Almost Empty : When asserted, this signal indicates that
|
// only one more read can be performed before the FIFO goes to empty.
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// only one more read can be performed before the FIFO goes to empty.
|
