URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

Subversion Repositories mpmc8

[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_mask_select.sv] - Diff between revs 7 and 10

Rev 7	Rev 10
Line 34...	Line 34...
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
`import mpmc10_pkg::*;`	`import mpmc10_pkg::*;`

`module mpmc10_mask_select(rst, clk, state, wmask, mask, mask2);`	`module mpmc10_mask_select(rst, clk, state, we, wmask, mask, mask2);`
`input rst;`	`input rst;`
`input clk;`	`input clk;`
`input mpmc10_state_t state;`	`input mpmc10_state_t state;`
	`input we;`
`input [15:0] wmask;`	`input [15:0] wmask;`
`output reg [15:0] mask;`	`output reg [15:0] mask;`
`output reg [15:0] mask2;`	`output reg [15:0] mask2;`

`// Setting the data mask. Values are enabled when the data mask is zero.`	`// Setting the data mask. Values are enabled when the data mask is zero.`
`always_ff @(posedge clk)`	`always_ff @(posedge clk)`
`if (rst)`	`if (rst)`
`mask2 <= 16'h0000;`	`mask2 <= 16'h0000;`
`else begin`	`else begin`
`if (state==PRESET2)`	`if (state==PRESET2)`
`mask2 <= wmask;`	`mask2 <= we ? ~wmask : 16'h0000;`
`// For RMW cycle all bytes are writtten.`	`// For RMW cycle all bytes are writtten.`
`else if (state==WRITE_TRAMP1)`	`else if (state==WRITE_TRAMP1)`
`mask2 <= 16'h0000;`	`mask2 <= 16'h0000;`
`end`	`end`
`always_ff @(posedge clk)`	`always_ff @(posedge clk)`