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https://opencores.org/ocsvn/mpmc8/mpmc8/trunk
[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_pkg.sv] - Diff between revs 9 and 11
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Rev 11 |
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2022-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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parameter CACHE_ASSOC = 4;
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parameter CACHE_ASSOC = 4;
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parameter RMW = 0;
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parameter RMW = 0;
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parameter NAR = 2;
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parameter NAR = 2;
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parameter AMSB = 28;
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parameter AMSB = 28;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter CMD_READ = 3'b001;
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parameter CMD_READ = 3'b001;
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parameter CMD_WRITE = 3'b000;
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parameter CMD_WRITE = 3'b000;
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// State machine states
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// State machine states
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typedef enum logic [3:0] {
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typedef enum logic [4:0] {
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IDLE = 4'd0,
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IDLE = 5'd0,
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PRESET1 = 4'd1,
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PRESET1 = 5'd1,
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PRESET2 = 4'd2,
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PRESET2 = 5'd2,
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WRITE_DATA0 = 4'd3,
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WRITE_DATA0 = 5'd3,
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WRITE_DATA1 = 4'd4,
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WRITE_DATA1 = 5'd4,
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WRITE_DATA2 = 4'd5,
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WRITE_DATA2 = 5'd5,
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WRITE_DATA3 = 4'd6,
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WRITE_DATA3 = 5'd6,
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READ_DATA = 4'd7,
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READ_DATA = 5'd7,
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READ_DATA0 = 4'd8,
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READ_DATA0 = 5'd8,
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READ_DATA1 = 4'd9,
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READ_DATA1 = 5'd9,
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READ_DATA2 = 4'd10,
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READ_DATA2 = 5'd10,
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WAIT_NACK = 4'd11,
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WAIT_NACK = 5'd11,
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WRITE_TRAMP = 4'd12, // write trampoline
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WRITE_TRAMP = 5'd12, // write trampoline
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WRITE_TRAMP1 = 4'd13,
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WRITE_TRAMP1 = 5'd13,
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PRESET3 = 4'd14
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PRESET3 = 5'd14,
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ALU = 5'd15,
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ALU1 = 5'd16,
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ALU2 = 5'd17,
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ALU3 = 5'd18,
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ALU4 = 5'd19,
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CAS = 5'd20
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} mpmc10_state_t;
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} mpmc10_state_t;
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typedef struct packed
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typedef struct packed
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{
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{
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logic [31:4] tag;
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logic [31:4] tag;
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