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Line 1... |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2015-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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Line 36... |
//
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//
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import mpmc10_pkg::*;
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import mpmc10_pkg::*;
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module mpmc10_state_machine_wb(rst, clk, calib_complete, to, rdy, wdf_rdy, fifo_empty,
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module mpmc10_state_machine_wb(rst, clk, calib_complete, to, rdy, wdf_rdy, fifo_empty,
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rd_rst_busy, fifo_out, state,
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rd_rst_busy, fifo_out, state,
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num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid);
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num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid, rmw_hit);
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input rst;
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input rst;
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input clk;
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input clk;
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input calib_complete;
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input calib_complete;
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input to; // state machine time-out
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input to; // state machine time-out
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input rdy;
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input rdy;
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input wdf_rdy;
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input wdf_rdy;
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input fifo_empty;
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input fifo_empty;
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input rd_rst_busy;
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input rd_rst_busy;
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input wb_write_request128_t fifo_out;
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input wb_cmd_request128_t fifo_out;
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output mpmc10_state_t state;
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output mpmc10_state_t state;
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input [5:0] num_strips;
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input [5:0] num_strips;
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input [5:0] req_strip_cnt;
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input [5:0] req_strip_cnt;
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input [5:0] resp_strip_cnt;
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input [5:0] resp_strip_cnt;
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input rd_data_valid;
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input rd_data_valid;
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input rmw_hit;
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mpmc10_state_t next_state;
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mpmc10_state_t next_state;
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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state <= next_state;
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state <= next_state;
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PRESET1:
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PRESET1:
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next_state <= PRESET2;
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next_state <= PRESET2;
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PRESET2:
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PRESET2:
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next_state <= PRESET3;
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next_state <= PRESET3;
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PRESET3:
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PRESET3:
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if (fifo_out.stb & fifo_out.we)
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if (fifo_out.stb && fifo_out.cmd==CMD_STORE)
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next_state <= WRITE_DATA0;
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next_state <= WRITE_DATA0;
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else
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else
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next_state <= READ_DATA0;
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next_state <= READ_DATA0;
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// Write data to the data fifo
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// Write command to the command fifo
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// Write occurs when app_wdf_wren is true and app_wdf_rdy is true
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// Write occurs when app_rdy is true
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WRITE_DATA0:
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WRITE_DATA0:
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// Issue a write command if the fifo is full.
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if (rdy)// && req_strip_cnt==num_strips)
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// if (!app_wdf_rdy)
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// next_state <= WRITE_DATA1;
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// else
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if (wdf_rdy)// && req_strip_cnt==num_strips)
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next_state <= WRITE_DATA1;
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next_state <= WRITE_DATA1;
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else
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else
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next_state <= WRITE_DATA0;
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next_state <= WRITE_DATA0;
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WRITE_DATA1:
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WRITE_DATA1:
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next_state <= WRITE_DATA2;
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next_state <= WRITE_DATA2;
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WRITE_DATA2:
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WRITE_DATA2:
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if (rdy)
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if (rdy)
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next_state <= WRITE_DATA3;
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next_state <= WRITE_DATA3;
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else
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else
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next_state <= WRITE_DATA2;
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next_state <= WRITE_DATA2;
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// Write data to the data fifo
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// Write occurs when app_wdf_wren is true and app_wdf_rdy is true
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WRITE_DATA3:
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WRITE_DATA3:
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if (wdf_rdy)
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next_state <= IDLE;
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next_state <= IDLE;
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else
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next_state <= WRITE_DATA3;
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// There could be multiple read requests submitted before any response occurs.
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// There could be multiple read requests submitted before any response occurs.
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// Stay in the SET_CMD_RD until all requested strips have been processed.
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// Stay in the SET_CMD_RD until all requested strips have been processed.
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READ_DATA0:
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READ_DATA0:
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next_state <= READ_DATA1;
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next_state <= READ_DATA1;
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next_state <= READ_DATA2;
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next_state <= READ_DATA2;
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else
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else
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next_state <= READ_DATA1;
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next_state <= READ_DATA1;
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// Wait for incoming responses, but only for so long to prevent a hang.
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// Wait for incoming responses, but only for so long to prevent a hang.
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READ_DATA2:
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READ_DATA2:
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if (rd_data_valid && resp_strip_cnt==num_strips)
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if (rd_data_valid && resp_strip_cnt==num_strips) begin
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case(fifo_out.cmd)
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CMD_LOAD,CMD_LOADZ:
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next_state <= WAIT_NACK;
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CMD_ADD,CMD_OR,CMD_AND,CMD_EOR,CMD_ASL,CMD_LSR,
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CMD_MIN,CMD_MAX,CMD_MINU,CMD_MAXU,CMD_CAS:
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next_state <= ALU;
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default:
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next_state <= WAIT_NACK;
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next_state <= WAIT_NACK;
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endcase
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end
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else
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else
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next_state <= READ_DATA2;
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next_state <= READ_DATA2;
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ALU:
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if (rmw_hit)
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next_state <= ALU1;
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ALU1:
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next_state <= ALU2;
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ALU2:
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next_state <= ALU3;
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ALU3:
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next_state <= ALU4;
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ALU4:
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next_state <= WRITE_TRAMP1;
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WRITE_TRAMP1:
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next_state <= WRITE_DATA0;
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WAIT_NACK:
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WAIT_NACK:
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// If we're not seeing a nack and there is a channel selected, then the
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// If we're not seeing a nack and there is a channel selected, then the
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// cache tag must not have updated correctly.
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// cache tag must not have updated correctly.
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// For writes, assume a nack by now.
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// For writes, assume a nack by now.
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next_state <= IDLE;
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next_state <= IDLE;
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