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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_state_machine_wb.sv] - Diff between revs 5 and 7

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//
//
// ============================================================================
// ============================================================================
//
//
import mpmc10_pkg::*;
import mpmc10_pkg::*;
 
 
module mpmc10_state_machine_wb(rst, clk, to, rdy, wdf_rdy, fifo_empty, rd_fifo,
module mpmc10_state_machine_wb(rst, clk, calib_complete, to, rdy, wdf_rdy, fifo_empty,
        rd_rst_busy, fifo_out, state,
        rd_rst_busy, fifo_out, state,
        num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid, wway);
        num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid);
input rst;
input rst;
input clk;
input clk;
 
input calib_complete;
input to;                                                       // state machine time-out
input to;                                                       // state machine time-out
input rdy;
input rdy;
input wdf_rdy;
input wdf_rdy;
input fifo_empty;
input fifo_empty;
input rd_rst_busy;
input rd_rst_busy;
output reg rd_fifo;
 
input wb_write_request128_t fifo_out;
input wb_write_request128_t fifo_out;
output reg [3:0] state;
output mpmc10_state_t state;
input [5:0] num_strips;
input [5:0] num_strips;
input [5:0] req_strip_cnt;
input [5:0] req_strip_cnt;
input [5:0] resp_strip_cnt;
input [5:0] resp_strip_cnt;
input rd_data_valid;
input rd_data_valid;
output reg [1:0] wway;
 
 
 
reg [3:0] next_state;
mpmc10_state_t next_state;
reg next_rd_fifo;
 
 
 
always_ff @(posedge clk)
always_ff @(posedge clk)
        state <= next_state;
        state <= next_state;
always_ff @(posedge clk)
 
        rd_fifo <= next_rd_fifo;
 
always_ff @(posedge clk)
 
if (rst)
 
        wway <= 2'd0;
 
else begin
 
        if (state==mpmc10_pkg::PRESET1)
 
                wway <= wway + 2'd1;
 
end
 
 
 
always_comb
always_comb
if (rst) begin
if (rst)
        next_state <= mpmc10_pkg::IDLE;
        next_state <= IDLE;
        next_rd_fifo <= 1'b0;
 
end
 
else begin
else begin
        next_rd_fifo <= 1'b0;
 
        case(state)
        case(state)
        mpmc10_pkg::IDLE:
        IDLE:
                if (!fifo_empty && !rd_rst_busy) begin
                if (!fifo_empty && !rd_rst_busy && calib_complete)
                        next_rd_fifo <= 1'b1;
                        next_state <= PRESET1;
                        next_state <= mpmc10_pkg::PRESET1;
                else
                end
                        next_state <= IDLE;
                else
        PRESET1:
                        next_state <= mpmc10_pkg::IDLE;
                next_state <= PRESET2;
        mpmc10_pkg::PRESET1:
        PRESET2:
                next_state <= mpmc10_pkg::PRESET2;
                next_state <= PRESET3;
        mpmc10_pkg::PRESET2:
        PRESET3:
                next_state <= mpmc10_pkg::PRESET3;
 
        mpmc10_pkg::PRESET3:
 
                if (fifo_out.stb & fifo_out.we)
                if (fifo_out.stb & fifo_out.we)
                        next_state <= mpmc10_pkg::WRITE_DATA0;
                        next_state <= WRITE_DATA0;
                else
                else
                        next_state <= mpmc10_pkg::READ_DATA0;
                        next_state <= READ_DATA0;
        // Write data to the data fifo
        // Write data to the data fifo
        // Write occurs when app_wdf_wren is true and app_wdf_rdy is true
        // Write occurs when app_wdf_wren is true and app_wdf_rdy is true
        mpmc10_pkg::WRITE_DATA0:
        WRITE_DATA0:
                // Issue a write command if the fifo is full.
                // Issue a write command if the fifo is full.
        //      if (!app_wdf_rdy)
        //      if (!app_wdf_rdy)
        //              next_state <= WRITE_DATA1;
        //              next_state <= WRITE_DATA1;
        //      else
        //      else
                if (wdf_rdy)// && req_strip_cnt==num_strips)
                if (wdf_rdy)// && req_strip_cnt==num_strips)
                        next_state <= mpmc10_pkg::WRITE_DATA1;
                        next_state <= WRITE_DATA1;
                else
                else
                        next_state <= mpmc10_pkg::WRITE_DATA0;
                        next_state <= WRITE_DATA0;
        mpmc10_pkg::WRITE_DATA1:
        WRITE_DATA1:
                next_state <= mpmc10_pkg::WRITE_DATA2;
                next_state <= WRITE_DATA2;
        mpmc10_pkg::WRITE_DATA2:
        WRITE_DATA2:
                if (rdy)
                if (rdy)
                        next_state <= mpmc10_pkg::WRITE_DATA3;
                        next_state <= WRITE_DATA3;
                else
                else
                        next_state <= mpmc10_pkg::WRITE_DATA2;
                        next_state <= WRITE_DATA2;
        mpmc10_pkg::WRITE_DATA3:
        WRITE_DATA3:
                next_state <= mpmc10_pkg::IDLE;
                next_state <= IDLE;
 
 
        // There could be multiple read requests submitted before any response occurs.
        // There could be multiple read requests submitted before any response occurs.
        // Stay in the SET_CMD_RD until all requested strips have been processed.
        // Stay in the SET_CMD_RD until all requested strips have been processed.
        mpmc10_pkg::READ_DATA0:
        READ_DATA0:
                next_state <= mpmc10_pkg::READ_DATA1;
                next_state <= READ_DATA1;
        // Could it take so long to do the request that we start getting responses
        // Could it take so long to do the request that we start getting responses
        // back?
        // back?
        mpmc10_pkg::READ_DATA1:
        READ_DATA1:
                if (rdy && req_strip_cnt==num_strips)
                if (rdy && req_strip_cnt==num_strips)
                        next_state <= mpmc10_pkg::READ_DATA2;
                        next_state <= READ_DATA2;
                else
                else
                        next_state <= mpmc10_pkg::READ_DATA1;
                        next_state <= READ_DATA1;
        // Wait for incoming responses, but only for so long to prevent a hang.
        // Wait for incoming responses, but only for so long to prevent a hang.
        mpmc10_pkg::READ_DATA2:
        READ_DATA2:
                if (rd_data_valid && resp_strip_cnt==num_strips)
                if (rd_data_valid && resp_strip_cnt==num_strips)
                        next_state <= mpmc10_pkg::WAIT_NACK;
                        next_state <= WAIT_NACK;
                else
                else
                        next_state <= mpmc10_pkg::READ_DATA2;
                        next_state <= READ_DATA2;
 
 
        mpmc10_pkg::WAIT_NACK:
        WAIT_NACK:
                // If we're not seeing a nack and there is a channel selected, then the
                // If we're not seeing a nack and there is a channel selected, then the
                // cache tag must not have updated correctly.
                // cache tag must not have updated correctly.
                // For writes, assume a nack by now.
                // For writes, assume a nack by now.
                next_state <= mpmc10_pkg::IDLE;
                next_state <= IDLE;
 
 
        default:        next_state <= mpmc10_pkg::IDLE;
        default:        next_state <= IDLE;
        endcase
        endcase
 
 
        // Is the state machine hung?
        // Is the state machine hung? Do not time out during calibration.
//      if (to)
        if (to && calib_complete)
//              next_state <= mpmc10_pkg::IDLE;
                next_state <= IDLE;
end
end
 
 
endmodule
endmodule

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