| Line 1... |
Line 1... |
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2015-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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| Line 30... |
Line 30... |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// 16000 LUTs, 130 BRAM (64kB cache)
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// 26500 LUTs, 130 BRAM (64kB cache)
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// 21400 LUTs no AMO
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//
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//
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// Read channels always wait until there is valid data in the cache.
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// Read channels always wait until there is valid data in the cache.
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// ============================================================================
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// ============================================================================
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//
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//
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//`define RED_SCREEN 1'b1
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//`define RED_SCREEN 1'b1
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`define SUPPORT_AMO 1'b1
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//`define SUPPORT_AMO_TETRA 1'b1
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//`define SUPPORT_AMO_OCTA 1'b1
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//`define SUPPORT_AMO_SHIFT 1'b1
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//`define SUPPORT_AMO_MULTI_SHIFT 1'b1
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|
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import wishbone_pkg::*;
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import wishbone_pkg::*;
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import mpmc10_pkg::*;
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import mpmc10_pkg::*;
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|
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module mpmc10_wb(
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module mpmc10_wb(
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| Line 61... |
Line 67... |
output app_wdf_wren,
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output app_wdf_wren,
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output app_wdf_end,
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output app_wdf_end,
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input [127:0] app_rd_data,
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input [127:0] app_rd_data,
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input app_rd_data_end,
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input app_rd_data_end,
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input ch0clk, ch1clk, ch2clk, ch3clk, ch4clk, ch5clk, ch6clk, ch7clk,
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input ch0clk, ch1clk, ch2clk, ch3clk, ch4clk, ch5clk, ch6clk, ch7clk,
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input wb_write_request128_t ch0i,
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input wb_cmd_request128_t ch0i,
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output wb_read_response128_t ch0o,
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output wb_cmd_response128_t ch0o,
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input wb_write_request128_t ch1i,
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input wb_cmd_request128_t ch1i,
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output wb_read_response128_t ch1o,
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output wb_cmd_response128_t ch1o,
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input wb_write_request128_t ch2i,
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input wb_cmd_request128_t ch2i,
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output wb_read_response128_t ch2o,
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output wb_cmd_response128_t ch2o,
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input wb_write_request128_t ch3i,
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input wb_cmd_request128_t ch3i,
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output wb_read_response128_t ch3o,
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output wb_cmd_response128_t ch3o,
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input wb_write_request128_t ch4i,
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input wb_cmd_request128_t ch4i,
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output wb_read_response128_t ch4o,
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output wb_cmd_response128_t ch4o,
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input wb_write_request128_t ch5i,
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input wb_cmd_request128_t ch5i,
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output wb_read_response128_t ch5o,
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output wb_cmd_response128_t ch5o,
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input wb_write_request128_t ch6i,
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input wb_cmd_request128_t ch6i,
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output wb_read_response128_t ch6o,
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output wb_cmd_response128_t ch6o,
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input wb_write_request128_t ch7i,
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input wb_cmd_request128_t ch7i,
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output wb_read_response128_t ch7o,
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output wb_cmd_response128_t ch7o,
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output mpmc10_state_t state
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output mpmc10_state_t state
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);
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);
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parameter NAR = 2; // Number of address reservations
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parameter NAR = 2; // Number of address reservations
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parameter CL = 3'd4; // Cache read latency
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parameter CL = 3'd4; // Cache read latency
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parameter STREAM0 = TRUE;
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parameter STREAM0 = 1'b1;
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parameter STREAM1 = FALSE;
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parameter STREAM1 = 1'b0;
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parameter STREAM2 = FALSE;
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parameter STREAM2 = 1'b0;
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parameter STREAM3 = FALSE;
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parameter STREAM3 = 1'b0;
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parameter STREAM4 = FALSE;
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parameter STREAM4 = 1'b0;
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parameter STREAM5 = TRUE;
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parameter STREAM5 = 1'b1;
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parameter STREAM6 = FALSE;
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parameter STREAM6 = 1'b0;
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parameter STREAM7 = FALSE;
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parameter STREAM7 = 1'b0;
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parameter RMW0 = 1'b0;
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wb_write_request128_t ch0is;
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parameter RMW1 = 1'b1;
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wb_write_request128_t ch0is2;
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parameter RMW2 = 1'b0;
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wb_write_request128_t ch1is;
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parameter RMW3 = 1'b0;
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wb_write_request128_t ch1is2;
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parameter RMW4 = 1'b0;
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wb_write_request128_t ch2is;
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parameter RMW5 = 1'b0;
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wb_write_request128_t ch2is2;
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parameter RMW6 = 1'b0;
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wb_write_request128_t ch3is;
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parameter RMW7 = 1'b1;
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wb_write_request128_t ch3is2;
|
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wb_write_request128_t ch4is;
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wb_cmd_request128_t ch0is;
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wb_write_request128_t ch4is2;
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wb_cmd_request128_t ch0is2;
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wb_write_request128_t ch5is;
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wb_cmd_request128_t ch1is;
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wb_write_request128_t ch5is2;
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wb_cmd_request128_t ch1is2;
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wb_write_request128_t ch6is;
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wb_cmd_request128_t ch2is;
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wb_write_request128_t ch6is2;
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wb_cmd_request128_t ch2is2;
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wb_write_request128_t ch7is;
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wb_cmd_request128_t ch3is;
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wb_write_request128_t ch7is2;
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wb_cmd_request128_t ch3is2;
|
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wb_cmd_request128_t ch4is;
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wb_read_response128_t ch0oa, ch0ob;
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wb_cmd_request128_t ch4is2;
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wb_read_response128_t ch1oa, ch1ob;
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wb_cmd_request128_t ch5is;
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wb_read_response128_t ch2oa, ch2ob;
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wb_cmd_request128_t ch5is2;
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wb_read_response128_t ch3oa, ch3ob;
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wb_cmd_request128_t ch6is;
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wb_read_response128_t ch4oa, ch4ob;
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wb_cmd_request128_t ch6is2;
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wb_read_response128_t ch5oa, ch5ob;
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wb_cmd_request128_t ch7is;
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wb_read_response128_t ch6oa, ch6ob;
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wb_cmd_request128_t ch7is2;
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wb_read_response128_t ch7oa, ch7ob;
|
|
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wb_cmd_response128_t ch0oa, ch0ob, ch0oc;
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assign ch0o = STREAM0 ? ch0ob : ch0oa;
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wb_cmd_response128_t ch1oa, ch1ob, ch1oc;
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assign ch1o = STREAM1 ? ch1ob : ch1oa;
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wb_cmd_response128_t ch2oa, ch2ob, ch2oc;
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assign ch2o = STREAM2 ? ch2ob : ch2oa;
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wb_cmd_response128_t ch3oa, ch3ob, ch3oc;
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assign ch3o = STREAM3 ? ch3ob : ch3oa;
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wb_cmd_response128_t ch4oa, ch4ob, ch4oc;
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assign ch4o = STREAM4 ? ch4ob : ch4oa;
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wb_cmd_response128_t ch5oa, ch5ob, ch5oc;
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assign ch5o = STREAM5 ? ch5ob : ch5oa;
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wb_cmd_response128_t ch6oa, ch6ob, ch6oc;
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assign ch6o = STREAM6 ? ch6ob : ch6oa;
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wb_cmd_response128_t ch7oa, ch7ob, ch7oc;
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assign ch7o = STREAM7 ? ch7ob : ch7oa;
|
|
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wire rmw0 = ch0is.cmd[4];
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wb_write_request128_t req_fifoi;
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wire rmw1 = ch1is.cmd[4];
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wb_write_request128_t req_fifoo;
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wire rmw2 = ch2is.cmd[4];
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wb_write_request128_t ld;
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wire rmw3 = ch3is.cmd[4];
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wb_write_request128_t fifo_mask;
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wire rmw4 = ch4is.cmd[4];
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wb_write_request128_t fifoo = req_fifoo & fifo_mask;
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wire rmw5 = ch5is.cmd[4];
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wire rmw6 = ch6is.cmd[4];
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wire rmw7 = ch7is.cmd[4];
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|
|
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assign ch0o = STREAM0 ? ch0ob : rmw0 ? ch0oc : ch0oa;
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assign ch1o = STREAM1 ? ch1ob : rmw1 ? ch1oc : ch1oa;
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assign ch2o = STREAM2 ? ch2ob : rmw2 ? ch2oc : ch2oa;
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assign ch3o = STREAM3 ? ch3ob : rmw3 ? ch3oc : ch3oa;
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assign ch4o = STREAM4 ? ch4ob : rmw4 ? ch4oc : ch4oa;
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assign ch5o = STREAM5 ? ch5ob : rmw5 ? ch5oc : ch5oa;
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assign ch6o = STREAM6 ? ch6ob : rmw6 ? ch6oc : ch6oa;
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assign ch7o = STREAM7 ? ch7ob : rmw7 ? ch7oc : ch7oa;
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|
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wb_cmd_request128_t req_fifoi;
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wb_cmd_request128_t req_fifoo;
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wb_cmd_request128_t ld;
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wb_cmd_request128_t fifo_mask;
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wb_cmd_request128_t fifoo = req_fifoo & fifo_mask;
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|
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genvar g;
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genvar g;
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integer n1,n2,n3;
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integer n1,n2,n3;
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wire v;
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wire full;
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wire empty;
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wire almost_full;
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wire almost_full;
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wire [4:0] cnt;
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wire [4:0] cnt;
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reg wr_fifo;
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reg wr_fifo;
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mpmc10_state_t prev_state;
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mpmc10_state_t prev_state;
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wire rd_fifo; // from state machine
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wire rd_fifo; // from state machine
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reg [5:0] num_strips; // from fifo
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reg [5:0] num_strips; // from fifo
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wire [5:0] req_strip_cnt;
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wire [5:0] req_strip_cnt;
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wire [5:0] resp_strip_cnt;
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wire [5:0] resp_strip_cnt;
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wire [15:0] tocnt;
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wire [15:0] tocnt;
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wire [31:0] app_waddr;
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reg [31:0] adr;
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reg [31:0] adr;
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reg [3:0] uch; // update channel
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reg [3:0] uch; // update channel
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wire [15:0] wmask;
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wire [15:0] wmask;
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wire [15:0] mem_wdf_mask2;
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wire [15:0] mem_wdf_mask2;
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reg [127:0] dat128;
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reg [127:0] dat128;
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| Line 155... |
Line 180... |
wire [31:0] resv_adr [0:NAR-1];
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wire [31:0] resv_adr [0:NAR-1];
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wire rb1;
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wire rb1;
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reg [7:0] req;
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reg [7:0] req;
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reg [127:0] rd_data_r;
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reg [127:0] rd_data_r;
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reg rd_data_valid_r;
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reg rd_data_valid_r;
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reg cas_ok;
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|
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wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
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wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
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wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
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wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
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wire ch0_hit_ne, ch5_hit_ne;
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wire ch0_hit_ne, ch5_hit_ne;
|
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wire hit0, hit1, hit2, hit3, hit4, hit5, hit6, hit7;
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|
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always_ff @(posedge mem_ui_clk)
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always_ff @(posedge mem_ui_clk)
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if (app_rd_data_valid)
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if (app_rd_data_valid)
|
rd_data_r <= app_rd_data;
|
rd_data_r <= app_rd_data;
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always_ff @(posedge mem_ui_clk)
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always_ff @(posedge mem_ui_clk)
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| Line 354... |
Line 381... |
// Streaming channels have a burst length of 64. Round the address to the burst
|
// Streaming channels have a burst length of 64. Round the address to the burst
|
// length.
|
// length.
|
always_comb
|
always_comb
|
begin
|
begin
|
ch0is2 <= ch0is;
|
ch0is2 <= ch0is;
|
ch0is2.adr <= {ch0is.adr[31:10],10'b0};
|
ch0is2.padr <= {ch0is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch1is2 <= ch1is;
|
ch1is2 <= ch1is;
|
ch1is2.adr <= {ch1is.adr[31:10],10'b0};
|
ch1is2.padr <= {ch1is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch2is2 <= ch2is;
|
ch2is2 <= ch2is;
|
ch2is2.adr <= {ch2is.adr[31:10],10'b0};
|
ch2is2.padr <= {ch2is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch3is2 <= ch3is;
|
ch3is2 <= ch3is;
|
ch3is2.adr <= {ch3is.adr[31:10],10'b0};
|
ch3is2.padr <= {ch3is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch4is2 <= ch4is;
|
ch4is2 <= ch4is;
|
ch4is2.adr <= {ch4is.adr[31:10],10'b0};
|
ch4is2.padr <= {ch4is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch5is2 <= ch5is;
|
ch5is2 <= ch5is;
|
ch5is2.adr <= {ch5is.adr[31:10],10'b0};
|
ch5is2.padr <= {ch5is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch6is2 <= ch6is;
|
ch6is2 <= ch6is;
|
ch6is2.adr <= {ch6is.adr[31:10],10'b0};
|
ch6is2.padr <= {ch6is.padr[31:10],10'b0};
|
end
|
end
|
always_comb
|
always_comb
|
begin
|
begin
|
ch7is2 <= ch7is;
|
ch7is2 <= ch7is;
|
ch7is2.adr <= {ch7is.adr[31:10],10'b0};
|
ch7is2.padr <= {ch7is.padr[31:10],10'b0};
|
end
|
end
|
|
|
always_comb
|
always_comb
|
begin
|
begin
|
ld.bte <= wishbone_pkg::LINEAR;
|
ld.bte <= wishbone_pkg::LINEAR;
|
ld.cti <= wishbone_pkg::CLASSIC;
|
ld.cti <= wishbone_pkg::CLASSIC;
|
ld.blen <= 'd0;
|
ld.blen <= 'd0;
|
ld.cyc <= fifoo.cyc && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
|
ld.cyc <= fifoo.cyc && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
|
ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
|
ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
|
ld.we <= 1'b0;
|
ld.we <= 1'b0;
|
ld.adr <= {app_waddr[31:4],4'h0};
|
ld.padr <= {app_waddr[31:4],4'h0};
|
ld.dat <= rd_data_r;
|
ld.data1 <= rd_data_r;
|
ld.sel <= {16{1'b1}}; // update all bytes
|
ld.sel <= {16{1'b1}}; // update all bytes
|
end
|
end
|
|
|
reg ch0wack;
|
reg ch0wack;
|
reg ch1wack;
|
reg ch1wack;
|
| Line 477... |
Line 504... |
.ch2o(ch2oa),
|
.ch2o(ch2oa),
|
.ch3o(ch3oa),
|
.ch3o(ch3oa),
|
.ch4o(ch4oa),
|
.ch4o(ch4oa),
|
.ch5o(ch5oa),
|
.ch5o(ch5oa),
|
.ch6o(ch6oa),
|
.ch6o(ch6oa),
|
.ch7o(ch7oa)
|
.ch7o(ch7oa),
|
|
.ch0hit(hit0),
|
|
.ch1hit(hit1),
|
|
.ch2hit(hit2),
|
|
.ch3hit(hit3),
|
|
.ch4hit(hit4),
|
|
.ch5hit(hit5),
|
|
.ch6hit(hit6),
|
|
.ch7hit(hit7)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm0
|
mpmc10_strm_read_cache ustrm0
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd0 && rd_data_valid_r),
|
.wr(uch==4'd0 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch0is.stb & ~ch0is.we),
|
.rd(ch0is.stb & ~ch0is.we),
|
.radr({ch0is.adr[31:4],4'h0}),
|
.radr({ch0is.padr[31:4],4'h0}),
|
.rdat(ch0ob.dat),
|
.rdat(ch0ob.dat),
|
.hit(ch0_hit_s)
|
.hit(ch0_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm1
|
mpmc10_strm_read_cache ustrm1
|
| Line 502... |
Line 537... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd1 && rd_data_valid_r),
|
.wr(uch==4'd1 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch1is.stb & ~ch1is.we),
|
.rd(ch1is.stb & ~ch1is.we),
|
.radr({ch1is.adr[31:4],4'h0}),
|
.radr({ch1is.padr[31:4],4'h0}),
|
.rdat(ch1ob.dat),
|
.rdat(ch1ob.dat),
|
.hit(ch1_hit_s)
|
.hit(ch1_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm2
|
mpmc10_strm_read_cache ustrm2
|
| Line 517... |
Line 552... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd2 && rd_data_valid_r),
|
.wr(uch==4'd2 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch2is.stb & ~ch2is.we),
|
.rd(ch2is.stb & ~ch2is.we),
|
.radr({ch2is.adr[31:4],4'h0}),
|
.radr({ch2is.padr[31:4],4'h0}),
|
.rdat(ch2ob.dat),
|
.rdat(ch2ob.dat),
|
.hit(ch2_hit_s)
|
.hit(ch2_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm3
|
mpmc10_strm_read_cache ustrm3
|
| Line 532... |
Line 567... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd3 && rd_data_valid_r),
|
.wr(uch==4'd3 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch3is.stb & ~ch3is.we),
|
.rd(ch3is.stb & ~ch3is.we),
|
.radr({ch3is.adr[31:4],4'h0}),
|
.radr({ch3is.padr[31:4],4'h0}),
|
.rdat(ch3ob.dat),
|
.rdat(ch3ob.dat),
|
.hit(ch3_hit_s)
|
.hit(ch3_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm4
|
mpmc10_strm_read_cache ustrm4
|
| Line 547... |
Line 582... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd4 && rd_data_valid_r),
|
.wr(uch==4'd4 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch4is.stb & ~ch4is.we),
|
.rd(ch4is.stb & ~ch4is.we),
|
.radr({ch4is.adr[31:4],4'h0}),
|
.radr({ch4is.padr[31:4],4'h0}),
|
.rdat(ch4ob.dat),
|
.rdat(ch4ob.dat),
|
.hit(ch4_hit_s)
|
.hit(ch4_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm5
|
mpmc10_strm_read_cache ustrm5
|
| Line 562... |
Line 597... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd5 && rd_data_valid_r),
|
.wr(uch==4'd5 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch5is.stb & ~ch5is.we),
|
.rd(ch5is.stb & ~ch5is.we),
|
.radr({ch5is.adr[31:4],4'h0}),
|
.radr({ch5is.padr[31:4],4'h0}),
|
.rdat(ch5ob.dat),
|
.rdat(ch5ob.dat),
|
.hit(ch5_hit_s)
|
.hit(ch5_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm6
|
mpmc10_strm_read_cache ustrm6
|
| Line 577... |
Line 612... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd6 && rd_data_valid_r),
|
.wr(uch==4'd6 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch6is.stb & ~ch6is.we),
|
.rd(ch6is.stb & ~ch6is.we),
|
.radr({ch6is.adr[31:4],4'h0}),
|
.radr({ch6is.padr[31:4],4'h0}),
|
.rdat(ch6ob.dat),
|
.rdat(ch6ob.dat),
|
.hit(ch6_hit_s)
|
.hit(ch6_hit_s)
|
);
|
);
|
|
|
mpmc10_strm_read_cache ustrm7
|
mpmc10_strm_read_cache ustrm7
|
| Line 592... |
Line 627... |
.rst(rst),
|
.rst(rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.wr(uch==4'd7 && rd_data_valid_r),
|
.wr(uch==4'd7 && rd_data_valid_r),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wadr({app_waddr[31:4],4'h0}),
|
.wdat(rd_data_r),
|
.wdat(rd_data_r),
|
// .inv(1'b0),
|
.inv(1'b0),
|
.rclk(mem_ui_clk),
|
.rclk(mem_ui_clk),
|
.rd(ch7is.stb & ~ch7is.we),
|
.rd(ch7is.stb & ~ch7is.we),
|
.radr({ch7is.adr[31:4],4'h0}),
|
.radr({ch7is.padr[31:4],4'h0}),
|
.rdat(ch7ob.dat),
|
.rdat(ch7ob.dat),
|
.hit(ch7_hit_s)
|
.hit(ch7_hit_s)
|
);
|
);
|
|
|
always_comb ch0ob.ack = ch0_hit_s & ch0i.stb;
|
always_comb ch0ob.ack = ch0_hit_s & ch0i.stb;
|
| Line 668... |
Line 703... |
always_comb
|
always_comb
|
uch <= fifoo.cid;
|
uch <= fifoo.cid;
|
always_comb
|
always_comb
|
num_strips <= fifoo.blen;
|
num_strips <= fifoo.blen;
|
always_comb
|
always_comb
|
adr <= fifoo.adr;
|
adr <= fifoo.padr;
|
|
|
wire [2:0] app_addr3; // dummy to make up 32-bits
|
wire [2:0] app_addr3; // dummy to make up 32-bits
|
|
|
mpmc10_addr_gen uag1
|
mpmc10_addr_gen uag1
|
(
|
(
|
| Line 707... |
Line 742... |
.wmask(req_fifoo.sel[15:0]),
|
.wmask(req_fifoo.sel[15:0]),
|
.mask(app_wdf_mask),
|
.mask(app_wdf_mask),
|
.mask2(mem_wdf_mask2)
|
.mask2(mem_wdf_mask2)
|
);
|
);
|
|
|
|
wire [127:0] data128a;
|
|
wire [127:0] data128b;
|
|
|
mpmc10_data_select #(.WID(128)) uds1
|
mpmc10_data_select #(.WID(128)) uds1
|
(
|
(
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.state(state),
|
.state(state),
|
.dati(req_fifoo.dat),
|
.dati1(req_fifoo.data1),
|
.dato(dat256)
|
.dati2(req_fifoo.data2),
|
|
.dato1(data128a),
|
|
.dato2(data128b)
|
);
|
);
|
|
|
|
reg rmw_hit;
|
|
reg rmw_ack;
|
|
reg [127:0] opa, opa1, opb, opc, t1;
|
|
reg [127:0] rmw_dat;
|
|
`ifdef SUPPORT_AMO
|
always_comb
|
always_comb
|
dat128 <= dat256;//req_strip_cnt[0] ? dat256[255:128] : dat256[127:0];
|
case(req_fifoo.cid)
|
|
4'd0: rmw_hit = hit0;
|
|
4'd1: rmw_hit = hit1;
|
|
4'd2: rmw_hit = hit2;
|
|
4'd3: rmw_hit = hit3;
|
|
4'd4: rmw_hit = hit4;
|
|
4'd5: rmw_hit = hit5;
|
|
4'd6: rmw_hit = hit6;
|
|
4'd7: rmw_hit = hit7;
|
|
default: rmw_hit = 1'b1;
|
|
endcase
|
|
always_ff @(posedge mem_ui_clk)
|
|
opb <= data128a >> {req_fifoo.padr[4:0],3'b0};
|
|
always_ff @(posedge mem_ui_clk)
|
|
opc <= data128b >> {req_fifoo.padr[4:0],3'b0};
|
|
always_ff @(posedge mem_ui_clk)
|
|
case(req_fifoo.cid)
|
|
4'd0: opa1 <= ch0oa.dat;
|
|
4'd1: opa1 <= ch1oa.dat;
|
|
4'd2: opa1 <= ch2oa.dat;
|
|
4'd3: opa1 <= ch3oa.dat;
|
|
4'd4: opa1 <= ch4oa.dat;
|
|
4'd5: opa1 <= ch5oa.dat;
|
|
4'd6: opa1 <= ch6oa.dat;
|
|
4'd7: opa1 <= ch7oa.dat;
|
|
default: opa1 <= 'd0;
|
|
endcase
|
|
always_ff @(posedge mem_ui_clk)
|
|
opa <= opa1 >> {req_fifoo.padr[4:0],3'b0};
|
|
always_ff @(posedge mem_ui_clk)
|
|
case(req_fifoo.sz)
|
|
`ifdef SUPPORT_AMO_TETRA
|
|
wishbone_pkg::tetra:
|
|
case(req_fifoo.cmd)
|
|
CMD_ADD: t1 <= opa[31:0] + opb[31:0];
|
|
CMD_AND: t1 <= opa[31:0] & opb[31:0];
|
|
CMD_OR: t1 <= opa[31:0] | opb[31:0];
|
|
CMD_EOR: t1 <= opa[31:0] ^ opb[31:0];
|
|
`ifdef SUPPORT_AMO_SHIFT
|
|
CMD_ASL: t1 <= {opa[30:0],1'b0};
|
|
CMD_LSR: t1 <= {1'b0,opa[31:1]};
|
|
CMD_ROL: t1 <= {opa[30:0],opa[31]};
|
|
CMD_ROR: t1 <= {opa[0],opa[31:1]};
|
|
`endif
|
|
`ifdef SUPPORT_AMO_MULTI_SHIFT
|
|
CMD_ASL: t1 <= opa[31:0] << opb[4:0];
|
|
CMD_LSR: t1 <= opa[31:0] >> opb[4:0];
|
|
`endif
|
|
CMD_MINU: t1 <= opa[31:0] < opb[31:0] ? opa[31:0] : opb[31:0];
|
|
CMD_MAXU: t1 <= opa[31:0] > opb[31:0] ? opa[31:0] : opb[31:0];
|
|
CMD_MIN: t1 <= $signed(opa[31:0]) < $signed(opb[31:0]) ? opa[31:0] : opb[31:0];
|
|
CMD_MAX: t1 <= $signed(opa[31:0]) > $signed(opb[31:0]) ? opa[31:0] : opb[31:0];
|
|
CMD_CAS: t1 <= opa[31:0]==opb[31:0] ? opc[31:0] : opb[31:0];
|
|
default: t1 <= opa[31:0];
|
|
endcase
|
|
`endif
|
|
`ifdef SUPPORT_AMO_OCTA
|
|
wishbone_pkg::octa:
|
|
case(req_fifoo.cmd)
|
|
CMD_ADD: t1 <= opa[63:0] + opb[63:0];
|
|
CMD_AND: t1 <= opa[63:0] & opb[63:0];
|
|
CMD_OR: t1 <= opa[63:0] | opb[63:0];
|
|
CMD_EOR: t1 <= opa[63:0] ^ opb[63:0];
|
|
`ifdef SUPPORT_AMO_SHIFT
|
|
CMD_ASL: t1 <= {opa[62:0],1'b0};
|
|
CMD_LSR: t1 <= {1'b0,opa[63:1]};
|
|
CMD_ROL: t1 <= {opa[62:0],opa[63]};
|
|
CMD_ROR: t1 <= {opa[0],opa[63:1]};
|
|
`endif
|
|
`ifdef SUPPORT_AMO_MULTI_SHIFT
|
|
CMD_ASL: t1 <= opa[63:0] << opb[5:0];
|
|
CMD_LSR: t1 <= opa[63:0] >> opb[5:0];
|
|
`endif
|
|
CMD_MINU: t1 <= opa[63:0] < opb[63:0] ? opa[63:0] : opb[63:0];
|
|
CMD_MAXU: t1 <= opa[63:0] > opb[63:0] ? opa[63:0] : opb[63:0];
|
|
CMD_MIN: t1 <= $signed(opa[63:0]) < $signed(opb[63:0]) ? opa[63:0] : opb[63:0];
|
|
CMD_MAX: t1 <= $signed(opa[63:0]) > $signed(opb[63:0]) ? opa[63:0] : opb[63:0];
|
|
CMD_CAS: t1 <= opa[63:0]==opb[63:0] ? opc[63:0] : opb[63:0];
|
|
default: t1 <= opa[63:0];
|
|
endcase
|
|
`endif
|
|
default:
|
|
case(req_fifoo.cmd)
|
|
CMD_ADD: t1 <= opa[127:0] + opb[127:0];
|
|
CMD_AND: t1 <= opa[127:0] & opb[127:0];
|
|
CMD_OR: t1 <= opa[127:0] | opb[127:0];
|
|
CMD_EOR: t1 <= opa[127:0] ^ opb[127:0];
|
|
`ifdef SUPPORT_AMO_SHIFT
|
|
CMD_ASL: t1 <= {opa[126:0],1'b0};
|
|
CMD_LSR: t1 <= {1'b0,opa[127:1]};
|
|
CMD_ROL: t1 <= {opa[126:0],opa[127]};
|
|
CMD_ROR: t1 <= {opa[0],opa[127:1]};
|
|
`endif
|
|
`ifdef SUPPORT_AMO_MULTI_SHIFT
|
|
CMD_ASL: t1 <= opa[127:0] << opb[6:0];
|
|
CMD_LSR: t1 <= opa[127:0] >> opb[6:0];
|
|
`endif
|
|
CMD_MINU: t1 <= opa[127:0] < opb[127:0] ? opa[127:0] : opb[127:0];
|
|
CMD_MAXU: t1 <= opa[127:0] > opb[127:0] ? opa[127:0] : opb[127:0];
|
|
CMD_MIN: t1 <= $signed(opa[127:0]) < $signed(opb[127:0]) ? opa[127:0] : opb[127:0];
|
|
CMD_MAX: t1 <= $signed(opa[127:0]) > $signed(opb[127:0]) ? opa[127:0] : opb[127:0];
|
|
CMD_CAS: t1 <= opa[127:0]==opb[127:0] ? opc[127:0] : opb[127:0];
|
|
default: t1 <= opa[127:0];
|
|
endcase
|
|
endcase
|
|
always_ff @(posedge mem_ui_clk)
|
|
rmw_dat <= t1 << {req_fifoo.padr[4:0],3'b0};
|
|
|
|
always_ff @(posedge mem_ui_clk)
|
|
if (mem_ui_rst) begin
|
|
ch0oc.dat <= 'd0;
|
|
ch1oc.dat <= 'd0;
|
|
ch2oc.dat <= 'd0;
|
|
ch3oc.dat <= 'd0;
|
|
ch4oc.dat <= 'd0;
|
|
ch5oc.dat <= 'd0;
|
|
ch6oc.dat <= 'd0;
|
|
ch7oc.dat <= 'd0;
|
|
end
|
|
else begin
|
|
if (state==WRITE_TRAMP1)
|
|
case(req_fifoo.cid)
|
|
4'd0: ch0oc.dat <= opa;
|
|
4'd1: ch1oc.dat <= opa;
|
|
4'd2: ch2oc.dat <= opa;
|
|
4'd3: ch3oc.dat <= opa;
|
|
4'd4: ch4oc.dat <= opa;
|
|
4'd5: ch5oc.dat <= opa;
|
|
4'd6: ch6oc.dat <= opa;
|
|
4'd7: ch7oc.dat <= opa;
|
|
default: ;
|
|
endcase
|
|
end
|
|
always_ff @(posedge mem_ui_clk)
|
|
if (mem_ui_rst)
|
|
rmw_ack <= 1'b0;
|
|
else begin
|
|
if (state==WRITE_TRAMP1)
|
|
rmw_ack <= 1'b1;
|
|
else if (state==IDLE)
|
|
rmw_ack <= 1'b0;
|
|
end
|
|
always_comb ch0oc.ack = ch0i.stb & rmw_ack & rmw0 && req_fifoo.cid==4'd0;
|
|
always_comb ch1oc.ack = ch1i.stb & rmw_ack & rmw1 && req_fifoo.cid==4'd1;
|
|
always_comb ch2oc.ack = ch2i.stb & rmw_ack & rmw2 && req_fifoo.cid==4'd2;
|
|
always_comb ch3oc.ack = ch3i.stb & rmw_ack & rmw3 && req_fifoo.cid==4'd3;
|
|
always_comb ch4oc.ack = ch4i.stb & rmw_ack & rmw4 && req_fifoo.cid==4'd4;
|
|
always_comb ch5oc.ack = ch5i.stb & rmw_ack & rmw5 && req_fifoo.cid==4'd5;
|
|
always_comb ch6oc.ack = ch6i.stb & rmw_ack & rmw6 && req_fifoo.cid==4'd6;
|
|
always_comb ch7oc.ack = ch7i.stb & rmw_ack & rmw7 && req_fifoo.cid==4'd7;
|
|
`endif
|
|
|
// Setting the data value. Unlike reads there is only a single strip involved.
|
// Setting the data value. Unlike reads there is only a single strip involved.
|
// Force unselected byte lanes to $FF
|
// Force unselected byte lanes to $FF
|
reg [127:0] dat128x;
|
reg [127:0] dat128x;
|
generate begin
|
generate begin
|
for (g = 0; g < 16; g = g + 1)
|
for (g = 0; g < 16; g = g + 1)
|
always_comb
|
always_comb
|
if (mem_wdf_mask2[g])
|
if (mem_wdf_mask2[g])
|
dat128x[g*8+7:g*8] = 8'hFF;
|
dat128x[g*8+7:g*8] = 8'hFF;
|
else
|
else
|
dat128x[g*8+7:g*8] = dat128[g*8+7:g*8];
|
dat128x[g*8+7:g*8] = data128a[g*8+7:g*8];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always_ff @(posedge mem_ui_clk)
|
always_ff @(posedge mem_ui_clk)
|
if (mem_ui_rst)
|
if (mem_ui_rst)
|
app_wdf_data <= 128'd0;
|
app_wdf_data <= 128'd0;
|
else begin
|
else begin
|
if (state==PRESET3)
|
if (state==PRESET3)
|
app_wdf_data <= dat128x;
|
app_wdf_data <= dat128x;
|
// else if (state==WRITE_TRAMP1)
|
else if (state==WRITE_TRAMP1)
|
// app_wdf_data <= rmw_data;
|
app_wdf_data <= rmw_dat;
|
end
|
end
|
|
|
mpmc10_rd_fifo_gen urdf1
|
mpmc10_rd_fifo_gen urdf1
|
(
|
(
|
.rst(rst|mem_ui_rst),
|
.rst(rst|mem_ui_rst),
|
| Line 777... |
Line 972... |
.fifo_out(req_fifoo),
|
.fifo_out(req_fifoo),
|
.state(state),
|
.state(state),
|
.num_strips(num_strips),
|
.num_strips(num_strips),
|
.req_strip_cnt(req_strip_cnt),
|
.req_strip_cnt(req_strip_cnt),
|
.resp_strip_cnt(resp_strip_cnt),
|
.resp_strip_cnt(resp_strip_cnt),
|
.rd_data_valid(rd_data_valid_r)
|
.rd_data_valid(rd_data_valid_r),
|
|
.rmw_hit(rmw_hit)
|
);
|
);
|
|
|
mpmc10_to_cnt utoc1
|
mpmc10_to_cnt utoc1
|
(
|
(
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
| Line 857... |
Line 1053... |
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.state(state),
|
.state(state),
|
.wch(fifoo.cid),
|
.wch(fifoo.cid),
|
.we(fifoo.stb & fifoo.we),
|
.we(fifoo.stb & fifoo.we),
|
.cr(fifoo.csr & fifoo.we),
|
.cr(fifoo.csr & fifoo.we),
|
.adr(fifoo.adr),
|
.adr(fifoo.padr),
|
.resv_ch(resv_ch),
|
.resv_ch(resv_ch),
|
.resv_adr(resv_adr),
|
.resv_adr(resv_adr),
|
.rb(rb1)
|
.rb(rb1)
|
);
|
);
|
|
|
| Line 869... |
Line 1065... |
(
|
(
|
.rst(mem_ui_rst),
|
.rst(mem_ui_rst),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.state(state),
|
.state(state),
|
.adr0(32'h0),
|
.adr0(32'h0),
|
.adr1(ch1is.adr),
|
.adr1(ch1is.padr),
|
.adr2(ch2is.adr),
|
.adr2(ch2is.padr),
|
.adr3(ch3is.adr),
|
.adr3(ch3is.padr),
|
.adr4(ch4is.adr),
|
.adr4(ch4is.padr),
|
.adr5(32'h0),
|
.adr5(32'h0),
|
.adr6(ch6is.adr),
|
.adr6(ch6is.padr),
|
.adr7(ch7is.adr),
|
.adr7(ch7is.padr),
|
.sr0(1'b0),
|
.sr0(1'b0),
|
.sr1(ch1is.csr & ch1is.stb & ~ch1is.we),
|
.sr1(ch1is.csr & ch1is.stb & ~ch1is.we),
|
.sr2(ch2is.csr & ch2is.stb & ~ch2is.we),
|
.sr2(ch2is.csr & ch2is.stb & ~ch2is.we),
|
.sr3(ch3is.csr & ch3is.stb & ~ch3is.we),
|
.sr3(ch3is.csr & ch3is.stb & ~ch3is.we),
|
.sr4(ch4is.csr & ch4is.stb & ~ch4is.we),
|
.sr4(ch4is.csr & ch4is.stb & ~ch4is.we),
|
.sr5(1'b0),
|
.sr5(1'b0),
|
.sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
|
.sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
|
.sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
|
.sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
|
.wch(fifoo.stb ? fifoo.cid : 4'd15),
|
.wch(fifoo.stb ? fifoo.cid : 4'd15),
|
.we(fifoo.stb & fifoo.we),
|
.we(fifoo.stb & fifoo.we),
|
.wadr(fifoo.adr),
|
.wadr(fifoo.padr),
|
.cr(fifoo.csr & fifoo.stb & fifoo.we),
|
.cr(fifoo.csr & fifoo.stb & fifoo.we),
|
.resv_ch(resv_ch),
|
.resv_ch(resv_ch),
|
.resv_adr(resv_adr)
|
.resv_adr(resv_adr)
|
);
|
);
|
|
|
