| Line 45... |
Line 45... |
module mpmc10_wb(
|
module mpmc10_wb(
|
input rst,
|
input rst,
|
input clk100MHz,
|
input clk100MHz,
|
input mem_ui_rst,
|
input mem_ui_rst,
|
input mem_ui_clk,
|
input mem_ui_clk,
|
|
input calib_complete,
|
output reg rstn,
|
output reg rstn,
|
output [31:0] app_waddr,
|
output [31:0] app_waddr,
|
input app_rdy,
|
input app_rdy,
|
output app_en,
|
output app_en,
|
output [2:0] app_cmd,
|
output [2:0] app_cmd,
|
| Line 76... |
Line 77... |
output wb_read_response128_t ch5o,
|
output wb_read_response128_t ch5o,
|
input wb_write_request128_t ch6i,
|
input wb_write_request128_t ch6i,
|
output wb_read_response128_t ch6o,
|
output wb_read_response128_t ch6o,
|
input wb_write_request128_t ch7i,
|
input wb_write_request128_t ch7i,
|
output wb_read_response128_t ch7o,
|
output wb_read_response128_t ch7o,
|
output [3:0] state
|
output mpmc10_state_t state
|
);
|
);
|
parameter NAR = 2; // Number of address reservations
|
parameter NAR = 2; // Number of address reservations
|
parameter CL = 3'd4; // Cache read latency
|
parameter CL = 3'd4; // Cache read latency
|
parameter STREAM0 = TRUE;
|
parameter STREAM0 = TRUE;
|
parameter STREAM1 = FALSE;
|
parameter STREAM1 = FALSE;
|
| Line 127... |
Line 128... |
assign ch7o = STREAM7 ? ch7ob : ch7oa;
|
assign ch7o = STREAM7 ? ch7ob : ch7oa;
|
|
|
wb_write_request128_t req_fifoi;
|
wb_write_request128_t req_fifoi;
|
wb_write_request128_t req_fifoo;
|
wb_write_request128_t req_fifoo;
|
wb_write_request128_t ld;
|
wb_write_request128_t ld;
|
|
wb_write_request128_t fifo_mask;
|
|
wb_write_request128_t fifoo = req_fifoo & fifo_mask;
|
|
|
genvar g;
|
genvar g;
|
integer n1,n2;
|
integer n1,n2,n3;
|
wire almost_full;
|
wire almost_full;
|
wire [4:0] cnt;
|
wire [4:0] cnt;
|
reg wr_fifo;
|
reg wr_fifo;
|
wire [3:0] prev_state;
|
mpmc10_state_t prev_state;
|
wire [3:0] state;
|
|
wire rd_fifo; // from state machine
|
wire rd_fifo; // from state machine
|
reg [5:0] num_strips; // from fifo
|
reg [5:0] num_strips; // from fifo
|
wire [5:0] req_strip_cnt;
|
wire [5:0] req_strip_cnt;
|
wire [5:0] resp_strip_cnt;
|
wire [5:0] resp_strip_cnt;
|
wire [15:0] tocnt;
|
wire [15:0] tocnt;
|
| Line 146... |
Line 148... |
reg [31:0] adr;
|
reg [31:0] adr;
|
reg [3:0] uch; // update channel
|
reg [3:0] uch; // update channel
|
wire [15:0] wmask;
|
wire [15:0] wmask;
|
wire [15:0] mem_wdf_mask2;
|
wire [15:0] mem_wdf_mask2;
|
reg [127:0] dat128;
|
reg [127:0] dat128;
|
wire [255:0] dat256;
|
wire [127:0] dat256;
|
wire [3:0] resv_ch [0:NAR-1];
|
wire [3:0] resv_ch [0:NAR-1];
|
wire [31:0] resv_adr [0:NAR-1];
|
wire [31:0] resv_adr [0:NAR-1];
|
wire rb1;
|
wire rb1;
|
reg [7:0] req;
|
reg [7:0] req;
|
wire [1:0] wway;
|
|
reg [127:0] rd_data_r;
|
reg [127:0] rd_data_r;
|
reg rd_data_valid_r;
|
reg rd_data_valid_r;
|
|
|
wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
|
wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
|
wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
|
wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
|
| Line 200... |
Line 201... |
end
|
end
|
else
|
else
|
chcnt[n2] <= 'd0;
|
chcnt[n2] <= 'd0;
|
end
|
end
|
|
|
reg [7:0] pe_req;
|
wire [7:0] pe_req;
|
reg [7:0] chack;
|
reg [7:0] chack;
|
always_comb chack[0] = ch0o.ack;
|
always_comb chack[0] = ch0o.ack;
|
always_comb chack[1] = ch1o.ack;
|
always_comb chack[1] = ch1o.ack;
|
always_comb chack[2] = ch2o.ack;
|
always_comb chack[2] = ch2o.ack;
|
always_comb chack[3] = ch3o.ack;
|
always_comb chack[3] = ch3o.ack;
|
always_comb chack[4] = ch4o.ack;
|
always_comb chack[4] = ch4o.ack;
|
always_comb chack[5] = ch5o.ack;
|
always_comb chack[5] = ch5o.ack;
|
always_comb chack[6] = ch6o.ack;
|
always_comb chack[6] = ch6o.ack;
|
always_comb chack[7] = ch7o.ack;
|
always_comb chack[7] = ch7o.ack;
|
|
|
|
reg [7:0] reqa;
|
|
always_comb reqa[1] = (!ch1o.ack && ch1is.stb && !ch1is.we && chcnt[1]==CL) || (ch1is.we && ch1is.stb);
|
|
always_comb reqa[5] = (!ch5o.ack && ch5is.stb && !ch5is.we && chcnt[5]==CL) || (ch5is.we && ch5is.stb);
|
|
|
|
wire rste = mem_ui_rst||rst||!calib_complete;
|
|
|
edge_det edch0 (
|
edge_det edch0 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch0o.ack && ch0is.stb && !ch0is.we && chcnt[0]==CL) || (ch0is.we && ch0is.stb)),
|
.i((!ch0o.ack && ch0is.stb && !ch0is.we && chcnt[0]==CL) || (ch0is.we && ch0is.stb)),
|
.pe(pe_req[0]),
|
.pe(pe_req[0]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch1 (
|
edge_det edch1 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch1o.ack && ch1is.stb && !ch1is.we && chcnt[1]==CL) || (ch1is.we && ch1is.stb)),
|
.i(reqa[1]),
|
.pe(pe_req[1]),
|
.pe(pe_req[1]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch2 (
|
edge_det edch2 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch2o.ack && ch2is.stb && !ch2is.we && chcnt[2]==CL) || (ch2is.we && ch2is.stb)),
|
.i((!ch2o.ack && ch2is.stb && !ch2is.we && chcnt[2]==CL) || (ch2is.we && ch2is.stb)),
|
.pe(pe_req[2]),
|
.pe(pe_req[2]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch3 (
|
edge_det edch3 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch3o.ack && ch3is.stb && !ch3is.we && chcnt[3]==CL) || (ch3is.we && ch3is.stb)),
|
.i((!ch3o.ack && ch3is.stb && !ch3is.we && chcnt[3]==CL) || (ch3is.we && ch3is.stb)),
|
.pe(pe_req[3]),
|
.pe(pe_req[3]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch4 (
|
edge_det edch4 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch4o.ack && ch4is.stb && !ch4is.we && chcnt[4]==CL) || (ch4is.we && ch4is.stb)),
|
.i((!ch4o.ack && ch4is.stb && !ch4is.we && chcnt[4]==CL) || (ch4is.we && ch4is.stb)),
|
.pe(pe_req[4]),
|
.pe(pe_req[4]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch5 (
|
edge_det edch5 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch5_hit_s && ch5is.stb && !ch5is.we && chcnt[5]==CL) || (ch5is.we && ch5is.stb)),
|
.i(reqa[5]),
|
.pe(pe_req[5]),
|
.pe(pe_req[5]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch6 (
|
edge_det edch6 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch6o.ack && ch6is.stb && !ch6is.we && chcnt[6]==CL) || (ch6is.we && ch6is.stb)),
|
.i((!ch6o.ack && ch6is.stb && !ch6is.we && chcnt[6]==CL) || (ch6is.we && ch6is.stb)),
|
.pe(pe_req[6]),
|
.pe(pe_req[6]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
edge_det edch7 (
|
edge_det edch7 (
|
.rst(mem_ui_rst),
|
.rst(rste),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.ce(1'b1),
|
.ce(1'b1),
|
.i((!ch7o.ack && ch7is.stb && !ch7is.we && chcnt[7]==CL) || (ch7is.we && ch7is.stb)),
|
.i((!ch7o.ack && ch7is.stb && !ch7is.we && chcnt[7]==CL) || (ch7is.we && ch7is.stb)),
|
.pe(pe_req[7]),
|
.pe(pe_req[7]),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
wire [3:0] req_sel;
|
wire [3:0] req_sel;
|
generate begin : gReq
|
|
for (g = 0; g < 8; g = g + 1)
|
|
always_ff @(posedge mem_ui_clk)
|
always_ff @(posedge mem_ui_clk)
|
if (pe_req[g])
|
for (n3 = 0; n3 < 8; n3 = n3 + 1)
|
req[g] <= 1'b1;
|
if (pe_req[n3])
|
else if (req_sel==g[3:0] || chack[g])
|
req[n3] <= 1'b1;
|
req[g] <= 1'b0;
|
else if ((req_sel==n3[3:0]) || chack[n3])
|
end
|
req[n3] <= 1'b0;
|
endgenerate
|
|
|
|
// Register signals onto mem_ui_clk domain
|
// Register signals onto mem_ui_clk domain
|
mpmc10_sync128_wb usyn0
|
mpmc10_sync128_wb usyn0
|
(
|
(
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
| Line 392... |
Line 396... |
always_comb
|
always_comb
|
begin
|
begin
|
ld.bte <= wishbone_pkg::LINEAR;
|
ld.bte <= wishbone_pkg::LINEAR;
|
ld.cti <= wishbone_pkg::CLASSIC;
|
ld.cti <= wishbone_pkg::CLASSIC;
|
ld.blen <= 'd0;
|
ld.blen <= 'd0;
|
ld.cyc <= req_fifoo.stb && !req_fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5);
|
ld.cyc <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
|
ld.stb <= req_fifoo.stb && !req_fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5);
|
ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
|
ld.we <= 1'b0;
|
ld.we <= 1'b0;
|
ld.adr <= {app_waddr[31:4],4'h0};
|
ld.adr <= {app_waddr[31:4],4'h0};
|
ld.dat <= {app_waddr[31:14],8'h00,rd_data_r}; // modified=false,tag = high order address bits
|
ld.dat <= {app_waddr[31:14],8'h00,rd_data_r}; // modified=false,tag = high order address bits
|
ld.sel <= {36{1'b1}}; // update all bytes
|
ld.sel <= {36{1'b1}}; // update all bytes
|
end
|
end
|
| Line 437... |
Line 441... |
|
|
mpmc10_cache_wb ucache1
|
mpmc10_cache_wb ucache1
|
(
|
(
|
.rst(mem_ui_rst),
|
.rst(mem_ui_rst),
|
.wclk(mem_ui_clk),
|
.wclk(mem_ui_clk),
|
.inv(),
|
.inv(1'b0),
|
.wchi(req_fifoo),
|
.wchi(fifoo),
|
.wcho(),
|
.wcho(),
|
.ld(ld),
|
.ld(ld),
|
.ch0clk(STREAM0 ? 1'b0 : ch0clk),
|
.ch0clk(STREAM0 ? 1'b0 : ch0clk),
|
.ch1clk(STREAM1 ? 1'b0 : ch1clk),
|
.ch1clk(STREAM1 ? 1'b0 : ch1clk),
|
.ch2clk(STREAM2 ? 1'b0 : ch2clk),
|
.ch2clk(STREAM2 ? 1'b0 : ch2clk),
|
| Line 608... |
Line 612... |
|
|
wire [7:0] sel;
|
wire [7:0] sel;
|
wire rd_rst_busy;
|
wire rd_rst_busy;
|
wire wr_rst_busy;
|
wire wr_rst_busy;
|
wire cd_sel;
|
wire cd_sel;
|
change_det #(.WID(8)) ucdsel (.rst(rst), .clk(mem_ui_clk), .i(sel), .cd(cd_sel));
|
change_det #(.WID(8)) ucdsel (.rst(rst), .ce(1'b1), .clk(mem_ui_clk), .i(sel), .cd(cd_sel));
|
|
|
always_comb //ff @(posedge mem_ui_clk)
|
always_comb //ff @(posedge mem_ui_clk)
|
wr_fifo = |sel & ~almost_full & ~wr_rst_busy & cd_sel;
|
wr_fifo = |sel & ~almost_full & ~wr_rst_busy & cd_sel;
|
|
|
roundRobin rr1
|
roundRobin rr1
|
| Line 634... |
Line 638... |
4'd3: req_fifoi <= STREAM3 ? ch3is2 : ch3is;
|
4'd3: req_fifoi <= STREAM3 ? ch3is2 : ch3is;
|
4'd4: req_fifoi <= STREAM4 ? ch4is2 : ch4is;
|
4'd4: req_fifoi <= STREAM4 ? ch4is2 : ch4is;
|
4'd5: req_fifoi <= STREAM5 ? ch5is2 : ch5is;
|
4'd5: req_fifoi <= STREAM5 ? ch5is2 : ch5is;
|
4'd6: req_fifoi <= STREAM6 ? ch6is2 : ch6is;
|
4'd6: req_fifoi <= STREAM6 ? ch6is2 : ch6is;
|
4'd7: req_fifoi <= STREAM7 ? ch7is2 : ch7is;
|
4'd7: req_fifoi <= STREAM7 ? ch7is2 : ch7is;
|
default: req_fifoi <= 'd0;
|
default:
|
|
begin
|
|
req_fifoi <= 'd0;
|
|
req_fifoi.cid <= 4'd15;
|
|
end
|
endcase
|
endcase
|
|
|
mpmc10_fifo ufifo1
|
mpmc10_fifo ufifo1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
| Line 655... |
Line 663... |
.wr_rst_busy(wr_rst_busy),
|
.wr_rst_busy(wr_rst_busy),
|
.cnt(cnt)
|
.cnt(cnt)
|
);
|
);
|
|
|
always_comb
|
always_comb
|
uch <= req_fifoo.cid;
|
uch <= fifoo.cid;
|
always_comb
|
always_comb
|
num_strips <= req_fifoo.blen;
|
num_strips <= fifoo.blen;
|
always_comb
|
always_comb
|
adr <= req_fifoo.adr;
|
adr <= fifoo.adr;
|
|
|
wire [2:0] app_addr3; // dummy to make up 32-bits
|
wire [2:0] app_addr3; // dummy to make up 32-bits
|
|
|
mpmc10_addr_gen uag1
|
mpmc10_addr_gen uag1
|
(
|
(
|
| Line 691... |
Line 699... |
|
|
mpmc10_set_write_mask_wb uswm1
|
mpmc10_set_write_mask_wb uswm1
|
(
|
(
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.state(state),
|
.state(state),
|
.we(req_fifoo.we),
|
.we(fifoo.we),
|
.sel(req_fifoo.sel[15:0]),
|
.sel(req_fifoo.sel[15:0]),
|
.adr(adr|{req_strip_cnt[0],4'h0}),
|
.adr(adr|{req_strip_cnt[0],4'h0}),
|
.mask(wmask)
|
.mask(wmask)
|
);
|
);
|
|
|
| Line 735... |
Line 743... |
|
|
always_ff @(posedge mem_ui_clk)
|
always_ff @(posedge mem_ui_clk)
|
if (mem_ui_rst)
|
if (mem_ui_rst)
|
app_wdf_data <= 128'd0;
|
app_wdf_data <= 128'd0;
|
else begin
|
else begin
|
if (state==PRESET2)
|
if (state==PRESET3)
|
app_wdf_data <= dat128x;
|
app_wdf_data <= dat128x;
|
// else if (state==WRITE_TRAMP1)
|
// else if (state==WRITE_TRAMP1)
|
// app_wdf_data <= rmw_data;
|
// app_wdf_data <= rmw_data;
|
end
|
end
|
|
|
|
mpmc10_rd_fifo_gen urdf1
|
|
(
|
|
.rst(rst|mem_ui_rst),
|
|
.clk(mem_ui_clk),
|
|
.state(state),
|
|
.empty(empty),
|
|
.rd_rst_busy(rd_rst_busy),
|
|
.calib_complete(calib_complete),
|
|
.rd(rd_fifo)
|
|
);
|
|
|
|
always_ff @(posedge mem_ui_clk)
|
|
if (rst)
|
|
fifo_mask <= 'd0;
|
|
else begin
|
|
if (rd_fifo)
|
|
fifo_mask <= {$bits(fifo_mask){1'b1}};
|
|
else if (state==IDLE)
|
|
fifo_mask <= 'd0;
|
|
end
|
|
|
mpmc10_state_machine_wb usm1
|
mpmc10_state_machine_wb usm1
|
(
|
(
|
.rst(rst|mem_ui_rst),
|
.rst(rst|mem_ui_rst),
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
|
.calib_complete(calib_complete),
|
.to(tocnt[9]),
|
.to(tocnt[9]),
|
.rdy(app_rdy),
|
.rdy(app_rdy),
|
.wdf_rdy(app_wdf_rdy),
|
.wdf_rdy(app_wdf_rdy),
|
.fifo_empty(empty),
|
.fifo_empty(empty),
|
.rd_rst_busy(rd_rst_busy),
|
.rd_rst_busy(rd_rst_busy),
|
.rd_fifo(rd_fifo),
|
|
.fifo_out(req_fifoo),
|
.fifo_out(req_fifoo),
|
.state(state),
|
.state(state),
|
.num_strips(num_strips),
|
.num_strips(num_strips),
|
.req_strip_cnt(req_strip_cnt),
|
.req_strip_cnt(req_strip_cnt),
|
.resp_strip_cnt(resp_strip_cnt),
|
.resp_strip_cnt(resp_strip_cnt),
|
| Line 834... |
Line 862... |
// Reservation status bit
|
// Reservation status bit
|
mpmc10_resv_bit ursb1
|
mpmc10_resv_bit ursb1
|
(
|
(
|
.clk(mem_ui_clk),
|
.clk(mem_ui_clk),
|
.state(state),
|
.state(state),
|
.wch(req_fifoo.cid),
|
.wch(fifoo.cid),
|
.we(req_fifoo.stb & req_fifoo.we),
|
.we(fifoo.stb & fifoo.we),
|
.cr(req_fifoo.csr & req_fifoo.we),
|
.cr(fifoo.csr & fifoo.we),
|
.adr(req_fifoo.adr),
|
.adr(fifoo.adr),
|
.resv_ch(resv_ch),
|
.resv_ch(resv_ch),
|
.resv_adr(resv_adr),
|
.resv_adr(resv_adr),
|
.rb(rb1)
|
.rb(rb1)
|
);
|
);
|
|
|
| Line 864... |
Line 892... |
.sr3(ch3is.csr & ch3is.stb & ~ch3is.we),
|
.sr3(ch3is.csr & ch3is.stb & ~ch3is.we),
|
.sr4(ch4is.csr & ch4is.stb & ~ch4is.we),
|
.sr4(ch4is.csr & ch4is.stb & ~ch4is.we),
|
.sr5(1'b0),
|
.sr5(1'b0),
|
.sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
|
.sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
|
.sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
|
.sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
|
.wch(req_fifoo.stb ? req_fifoo.cid : 4'd15),
|
.wch(fifoo.stb ? fifoo.cid : 4'd15),
|
.we(req_fifoo.stb & req_fifoo.we),
|
.we(fifoo.stb & fifoo.we),
|
.wadr(req_fifoo.adr),
|
.wadr(fifoo.adr),
|
.cr(req_fifoo.csr & req_fifoo.stb & req_fifoo.we),
|
.cr(fifoo.csr & fifoo.stb & fifoo.we),
|
.resv_ch(resv_ch),
|
.resv_ch(resv_ch),
|
.resv_adr(resv_adr)
|
.resv_adr(resv_adr)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
