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[/] [myblaze/] [trunk/] [rtl/] [bram.py] - Diff between revs 3 and 5

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Rev 3	Rev 5
Line 3...	Line 3...
`bram.py`	`bram.py`
`=======`	`=======`

`Block RAM`	`Block RAM`

`:copyright: Copyright (c) 2010 Jian Luo.`	`:copyright: Copyright (c) 2010 Jian Luo`
`:author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.`	`:author-email: jian.luo.cn(at_)gmail.com`
`:license: BSD, see LICENSE for details.`	`:license: LGPL, see LICENSE for details`
`:revision: $Id: bram.py 3 2010-11-21 07:17:00Z rockee $`	`:revision: $Id: bram.py 5 2010-11-21 10:59:30Z rockee $`
`"""`	`"""`

`from myhdl import *`	`from myhdl import *`
`from defines import *`	`from defines import *`
`from functions import *`	`from functions import *`
Line 81...	Line 81...
`enable,`	`enable,`
`clock,`	`clock,`
`width=32,`	`width=32,`
`bank_size=2,`	`bank_size=2,`
`size=16,`	`size=16,`
`to_verilog=False,`	`to_verilog=1,`
`filename_pattern='',`	`filename_pattern='',`
`):`	`):`
`# XXX: Verilog just don't allow dynamic register slicing`	`# XXX: Verilog just don't allow dynamic register slicing`
`# have to fix ram shape to 4x8bit`	`# have to fix ram shape to 4x8bit`
`if to_verilog:`	`if to_verilog == 1:`
`width=32`	`width=32`
`bank_size=2`	`bank_size=2`
`bank_count = 2 ** bank_size`	`bank_count = 2 ** bank_size`
`bank_width = width/bank_count`	`bank_width = width/bank_count`
`bank_in = [Signal(intbv(0)[bank_width:]) for i in range(bank_count)]`	`bank_in = [Signal(intbv(0)[bank_width:]) for i in range(bank_count)]`
Line 121...	Line 121...
`#if write:`	`#if write:`
`#print 'WRITE %x' % int(data_in)`	`#print 'WRITE %x' % int(data_in)`
`#else:`	`#else:`
`#print 'READ %x' % int(data_out)`	`#print 'READ %x' % int(data_out)`

`#if to_verilog:`	`if to_verilog == 1:`
`if 1:`
`@always_comb`	`@always_comb`
`def dumbass_reassemble():`	`def dumbass_reassemble():`
`bank_addr.next = address[:bank_size]`	`bank_addr.next = address[:bank_size]`
`for i in range(bank_count):`	`for i in range(bank_count):`
`bank_wre[i].next = write[i]`	`bank_wre[i].next = write[i]`

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[/] [myblaze/] [trunk/] [rtl/] [bram.py] - Diff between revs 3 and 5