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Line 6... |
Block RAM
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Block RAM
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:copyright: Copyright (c) 2010 Jian Luo
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:license: LGPL, see LICENSE for details
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:revision: $Id: bram.py 5 2010-11-21 10:59:30Z rockee $
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:revision: $Id: bram.py 6 2010-11-21 23:18:44Z rockee $
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"""
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"""
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from myhdl import *
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from myhdl import *
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from defines import *
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from defines import *
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from functions import *
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from functions import *
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| Line 54... |
Line 54... |
"""
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"""
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Single Port Synchronous RAM with Old Data Read-During-Write Behavior
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Single Port Synchronous RAM with Old Data Read-During-Write Behavior
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"""
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"""
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max = 2**size
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max = 2**size
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ram = RAM(Signal(intbv(0)[width:]) for i in range(max))
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ram = RAM(Signal(intbv(0)[width:]) for i in range(max))
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#read_addr = Signal(intbv(0)[len(address):])
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if filename:
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if filename:
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init = BRAMInitial(ram, filename, clock)
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init = BRAMInitial(ram, filename, clock)
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@always(clock.posedge)
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@always(clock.posedge)
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def logic():
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def logic():
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if enable:
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if enable:
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if write:
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if write:
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ram[int(address)].next = data_in
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ram[int(address)].next = data_in
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data_out.next = ram[int(address)%max]
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data_out.next = ram[int(address)%max]
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#read_addr.next = address
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#@always_comb
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#def output():
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#data_out.next = ram[int(read_addr)]
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return instances()
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return instances()
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def BankedBRAM(
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def BankedBRAM(
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data_out,
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data_out,
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| Line 86... |
Line 81... |
to_verilog=1,
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to_verilog=1,
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filename_pattern='',
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filename_pattern='',
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):
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):
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# XXX: Verilog just don't allow dynamic register slicing
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# XXX: Verilog just don't allow dynamic register slicing
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# have to fix ram shape to 4x8bit
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# have to fix ram shape to 4x8bit
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if to_verilog == 1:
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if to_verilog:
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width=32
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width=32
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bank_size=2
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bank_size=2
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bank_count = 2 ** bank_size
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bank_count = 2 ** bank_size
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bank_width = width/bank_count
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bank_width = width/bank_count
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bank_in = [Signal(intbv(0)[bank_width:]) for i in range(bank_count)]
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bank_in = [Signal(intbv(0)[bank_width:]) for i in range(bank_count)]
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| Line 111... |
Line 106... |
enable=enable, clock=clock,
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enable=enable, clock=clock,
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width=bank_width, size=size-bank_size,)
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width=bank_width, size=size-bank_size,)
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for i in range(bank_count)]
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for i in range(bank_count)]
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if to_verilog:
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#@always(clock.posedge)
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#def debug():
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#if enable and address==0x17f4:
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#print 'XXXXXX 17f4',
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#if write:
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#print 'WRITE %x' % int(data_in)
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#else:
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#print 'READ %x' % int(data_out)
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if to_verilog == 1:
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@always_comb
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@always_comb
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def dumbass_reassemble():
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def reassemble():
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bank_addr.next = address[:bank_size]
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bank_addr.next = address[:bank_size]
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for i in range(bank_count):
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for i in range(bank_count):
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bank_wre[i].next = write[i]
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bank_wre[i].next = write[i]
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#bank_in[3].next = data_in[8:]
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#bank_in[2].next = data_in[16:8]
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#bank_in[1].next = data_in[24:16]
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#bank_in[0].next = data_in[32:24]
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#data_out.next = concat(bank_out[0], bank_out[1],
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#bank_out[2], bank_out[3])
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bank_in[0].next = data_in[8:]
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bank_in[0].next = data_in[8:]
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bank_in[1].next = data_in[16:8]
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bank_in[1].next = data_in[16:8]
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bank_in[2].next = data_in[24:16]
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bank_in[2].next = data_in[24:16]
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bank_in[3].next = data_in[32:24]
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bank_in[3].next = data_in[32:24]
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data_out.next = concat(bank_out[3], bank_out[2],
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data_out.next = concat(bank_out[3], bank_out[2],
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bank_out[1], bank_out[0])
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bank_out[1], bank_out[0])
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#else:
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else:
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#@always_comb
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@always_comb
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#def reassemble():
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def reassemble():
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#bank_addr.next = address[:bank_size]
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bank_addr.next = address[:bank_size]
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#tmp = intbv(0)[width:]
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tmp = intbv(0)[width:]
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#tmp_low = intbv(0)[width-bank_width:]
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tmp_low = intbv(0)[width-bank_width:]
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#for i in range(bank_count):
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for i in range(bank_count):
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#bank_wre[i].next = write[i]
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bank_wre[i].next = write[i]
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#bank_in[i].next = data_in[(i+1)*bank_width:i*bank_width]
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bank_in[i].next = data_in[(i+1)*bank_width:i*bank_width]
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#tmp_low[:] = tmp[:bank_width]
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tmp_low[:] = tmp[:bank_width]
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#tmp[:] = concat(bank_out[i], tmp_low)
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tmp[:] = concat(bank_out[i], tmp_low)
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#data_out.next = tmp
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data_out.next = tmp
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return instances()
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return bank, reassemble
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if __name__ == '__main__':
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if __name__ == '__main__':
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data_out = Signal(intbv(0)[32:])
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data_out = Signal(intbv(0)[32:])
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data_in = Signal(intbv(0)[32:])
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data_in = Signal(intbv(0)[32:])
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address = Signal(intbv(0)[16:])
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address = Signal(intbv(0)[16:])
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| Line 176... |
Line 155... |
width=32,
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width=32,
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size=8,
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size=8,
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filename='rom.vmem',
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filename='rom.vmem',
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)
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)
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kw = dict(
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kw = dict(
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func=BankedBRAM,
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data_out=data_out,
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data_out=data_out,
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data_in=data_in,
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data_in=data_in,
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address=address,
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address=address,
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write=write,
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write=write,
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enable=enable,
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enable=enable,
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clock=clock,
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clock=clock,
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width=32,
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width=32,
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bank_size=2,
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bank_size=2,
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size=8,
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size=8,
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filename='rom.vmem',
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filename_pattern='rom%d.vmem',
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)
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)
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toVerilog(to_verilog=True, **kw)
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toVerilog(BankedBRAM, to_verilog=True, **kw)
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toVerilog(**bram_kw)
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#toVerilog(**bram_kw)
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toVHDL(**kw)
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toVHDL(BankedBRAM, **kw)
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### EOF ###
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### EOF ###
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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No newline at end of file
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No newline at end of file
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