| Line 136... |
Line 136... |
signal stateIO: IOType;
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signal stateIO: IOType;
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signal statetag: tType;
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signal statetag: tType;
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signal stateram: rType;
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signal stateram: rType;
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signal statequeue: fType;
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signal statequeue: fType;
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt: std_ulogic;
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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begin
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begin
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| Line 202... |
Line 202... |
if rising_edge(Clock) then
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if rising_edge(Clock) then
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if nReset /= '1' then
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if nReset /= '1' then
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statetag <= inittag;
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statetag <= inittag;
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writet <= '0';
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writet <= '0';
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enableram <= '0';
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enableram <= '0';
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oldint <= '0';
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found <= 15;
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found <= 15;
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free <= 15;
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free <= 15;
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done <= '0'; -- NEW
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done <= '0'; -- NEW
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initcount <= ( others => '0');
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initcount <= ( others => '0');
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AddressInt <= ( others => '0');
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AddressInt <= ( others => '0');
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IOCodeh <= ( others => '0');
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IOCodeh <= ( others => '0');
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AddressInh <= ( others => '0');
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AddressInh <= ( others => '0');
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else
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else
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oldint <= interrupt;
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case statetag is
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case statetag is
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when inittag =>
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when inittag =>
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for i in tagRAMIn'range loop
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for i in tagRAMIn'range loop
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tagRAMIn(i).tagValid <= '0';
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tagRAMIn(i).tagValid <= '0';
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tagRAMIn(i).tag <= ( others => '0');
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tagRAMIn(i).tag <= ( others => '0');
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| Line 262... |
Line 264... |
statetag <= tagwait;
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statetag <= tagwait;
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end if;
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end if;
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when tagwait =>
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when tagwait =>
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writet <= '0';
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writet <= '0';
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if interrupt = '1' then
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if interrupt = '1' and oldint = '0' then
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enableram <= '0';
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enableram <= '0';
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AddressInt <= toFlush;
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AddressInt <= toFlush;
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statetag <= stateget;
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statetag <= stateget;
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elsif queuedone = '1' then
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elsif queuedone = '1' then
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enableram <= '0';
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enableram <= '0';
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| Line 351... |
Line 353... |
FreeIn <= ( others => '0');
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FreeIn <= ( others => '0');
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firstf <= ( others => '0');
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firstf <= ( others => '0');
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lastf <= ( others => '0');
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lastf <= ( others => '0');
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counterf <= ( others => '0');
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counterf <= ( others => '0');
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else
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else
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hi := accinterrupt or interrupt;
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hi := accinterrupt or (interrupt and not oldint);
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acc := accqueue or queuedone;
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acc := accqueue or queuedone;
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en := enablequeue and ( hi nor acc);
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en := enablequeue and not acc;
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if ldCachedWords = 0 then
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if ldCachedWords = 0 then
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index := 0;
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index := 0;
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else
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else
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index := to_integer( AddressInh( ldCachedWords + 1 downto 2));
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index := to_integer( AddressInh( ldCachedWords + 1 downto 2));
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| Line 543... |
Line 545... |
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stateram <= ramflush1;
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stateram <= ramflush1;
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when ramflush1 =>
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when ramflush1 =>
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if writesh = '0' then
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if writesh = '0' then
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if del /= 15 and hi = '1' then
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if del /= 15 and hi = '1' then
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doneh <= '1';
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en := '1';
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hi := '0';
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hi := '0';
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stateram <= ramwait;
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stateram <= ramwait;
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else
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else
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tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
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tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
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tagBuff( elim).tagValid <= '1';
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tagBuff( elim).tagValid <= '1';
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| Line 648... |
Line 648... |
getAm <= '0'; -- NEW
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getAm <= '0'; -- NEW
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removeA1 <= '0'; -- NEW
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removeA1 <= '0'; -- NEW
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removeAm <= '0'; -- NEW
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removeAm <= '0'; -- NEW
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putA1 <= '0'; -- NEW
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putA1 <= '0'; -- NEW
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putAm <= '0'; -- NEW
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putAm <= '0'; -- NEW
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serviced <= '0';
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else
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else
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hi := '0';
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hi := interrupt;
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acc := accdone or doneh;
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acc := accdone or doneh;
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diff := firstA1 - unsigned( RecBuff.FiFoAddr);
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diff := firstA1 - unsigned( RecBuff.FiFoAddr);
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case statequeue is
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case statequeue is
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| Line 685... |
Line 686... |
A1Inaddr <= RecBuff.FiFoAddr;
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A1Inaddr <= RecBuff.FiFoAddr;
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removeA1 <= '1';
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removeA1 <= '1';
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statequeue <= queuewaitAm1;
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statequeue <= queuewaitAm1;
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end if;
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end if;
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elsif free /= 15 then
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elsif free /= 15 then
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if fullA1 = '1' or (emptyf = '1' and emptyA1 = '0') then
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if fullA1 = '1' or (emptyf = '1' and emptyA1 = '0' and serviced = '0') then
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-- remove last entry from A1
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-- remove last entry from A1
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if A1Out.valid = '1' then
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if A1Out.valid = '1' then
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del <= to_integer( A1Out.way);
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del <= to_integer( A1Out.way);
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toFlush <= A1Out.word;
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toFlush <= A1Out.word;
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getA1 <= '1';
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getA1 <= '1';
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hi := '1';
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hi := '1';
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serviced <= '1';
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statequeue <= queuewait;
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statequeue <= queuewait;
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end if;
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end if;
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elsif fullAm = '1' and emptyf = '1' then
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elsif fullAm = '1' and emptyf = '1' and serviced = '0' then
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-- remove last entry from Am
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-- remove last entry from Am
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if AmOut.valid = '1' then
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if AmOut.valid = '1' then
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del <= to_integer( AmOut.way);
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del <= to_integer( AmOut.way);
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toFlush <= AmOut.word;
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toFlush <= AmOut.word;
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getAm <= '1';
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getAm <= '1';
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hi := '1';
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hi := '1';
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serviced <= '1';
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statequeue <= queuewait;
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statequeue <= queuewait;
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end if;
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end if;
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else
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else
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A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
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A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
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A1In.way <= std_ulogic_vector(to_unsigned( free, ldways + 1));
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A1In.way <= std_ulogic_vector(to_unsigned( free, ldways + 1));
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A1In.valid <= '1';
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A1In.valid <= '1';
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putA1 <= '1';
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putA1 <= '1';
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serviced <= '0';
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statequeue <= queuewaitA11;
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statequeue <= queuewaitA11;
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end if;
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end if;
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elsif elim /= 15 then
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elsif elim /= 15 then
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if fullA1 = '1' then
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if fullA1 = '1' then
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if A1Out.valid = '1' then
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if A1Out.valid = '1' then
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| Line 740... |
Line 744... |
when queuewait =>
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when queuewait =>
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removeA1 <= '0';
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removeA1 <= '0';
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removeAm <= '0';
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removeAm <= '0';
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getAm <= '0';
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getAm <= '0';
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getA1 <= '0';
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getA1 <= '0';
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queuedone <= '0';
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if acc = '1' then
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if hi = '1' then
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hi := '0';
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statequeue <= queuestart;
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elsif acc = '1' then
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acc := '0';
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acc := '0';
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del <= 15;
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del <= 15;
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queuedone <= '0';
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statequeue <= queuestart;
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statequeue <= queuestart;
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end if;
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end if;
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when queuewaitAm1 =>
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when queuewaitAm1 =>
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putAm <= '0';
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putAm <= '0';
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removeA1 <= '0';
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removeA1 <= '0';
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