| Line 135... |
Line 135... |
signal found, free, elim, del: myint;
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signal found, free, elim, del: myint;
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signal stateIO: IOType;
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signal stateIO: IOType;
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signal statetag: tType;
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signal statetag: tType;
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signal stateram: rType;
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signal stateram: rType;
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signal statequeue: fType;
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signal statequeue: fType;
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag,
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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signal gal: std_ulogic_vector( 7 downto 0);
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signal gal: std_ulogic_vector( 7 downto 0);
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begin
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begin
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| Line 354... |
Line 354... |
getf <= '0';
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getf <= '0';
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putf <= '0'; -- NEW inserted
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putf <= '0'; -- NEW inserted
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doneh <= '0';
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doneh <= '0';
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accinterrupt <= '0';
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accinterrupt <= '0';
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accqueue <= '0';
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accqueue <= '0';
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isfull <= '0';
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flag <= '0';
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initcount1 <= ( others => '0');
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initcount1 <= ( others => '0');
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FreeIn <= ( others => '0');
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FreeIn <= ( others => '0');
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firstf <= ( others => '0');
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firstf <= ( others => '0');
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lastf <= ( others => '0');
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lastf <= ( others => '0');
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counterf <= ( others => '0');
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counterf <= ( others => '0');
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| Line 383... |
Line 385... |
else
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else
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putf <= '1';
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putf <= '1';
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end if;
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end if;
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when ramstart =>
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when ramstart =>
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if enableram = '1' then -- UPDATE
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if enableram = '1' then -- UPDATE
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if isfull = '0' then
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tagBuff <= tagRAMOut;
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tagBuff <= tagRAMOut;
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end if;
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if found /= 15 then
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if found /= 15 then
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cindex <= tagRAMOut( found).cacheAddr;
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cindex <= tagRAMOut( found).cacheAddr;
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isfull <= '0';
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stateram <= ramupdate;
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stateram <= ramupdate;
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elsif free /= 15 then
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elsif free /= 15 then
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en := '1';
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en := '1';
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if emptyf = '1' and isfull = '0' then
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isfull <= '1';
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stateram <= ramwait;
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stateram <= ramwait;
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else
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else
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cindex <= tagRAMOut( elim).cacheAddr;
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stateram <= ramupdate;
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end if;
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end if;
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when ramupdate =>
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stateram <= ramupdate1;
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when ramupdate1 =>
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cacheIn <= cacheOut;
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blockOut <= cacheOut.Words;
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RecBuff <= cacheOut;
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en := '1';
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stateram <= ramwait;
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when ramwait =>
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doneh <= '0';
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if hi = '1' then
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stateram <= ramwait1;
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elsif acc = '1' then
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if found /= 15 then
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cindex <= tagBuff( found).cacheAddr;
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cacheIn <= RecBuff;
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blockOut <= RecBuff.Words;
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stateram <= ramupdate2;
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elsif free /= 15 then
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cindex <= FreeOut;
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cindex <= FreeOut;
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tagBuff( free).cacheAddr <= FreeOut;
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tagBuff( free).cacheAddr <= FreeOut;
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tagBuff( free).cacheValid <= '1';
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tagBuff( free).cacheValid <= '1';
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tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
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tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
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tagBuff( free).tagValid <= '1';
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tagBuff( free).tagValid <= '1';
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isfull <= '0';
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getf <= '1';
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getf <= '1';
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if IOCodeh = "111" and ldCachedWords = 0 then
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if IOCodeh = "111" and ldCachedWords = 0 then
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stateram <= ramupdate2;
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stateram <= ramupdate2;
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else
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else
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readb <= '1';
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readb <= '1';
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AddressOut <= AddressInh( AddressOut'range);
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AddressOut <= AddressInh( AddressOut'range);
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stateram <= ramread;
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stateram <= ramread;
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end if;
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end if;
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end if;
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else
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cindex <= tagRAMOut( elim).cacheAddr;
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isfull <= '0';
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stateram <= ramupdate;
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end if;
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end if;
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when ramupdate =>
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stateram <= ramupdate1;
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when ramupdate1 =>
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cacheIn <= cacheOut;
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blockOut <= cacheOut.Words;
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RecBuff <= cacheOut;
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en := '1';
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if found /= 15 then
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stateram <= ramupdate2;
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else
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else
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cindex <= tagBuff( elim).cacheAddr;
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cacheIn <= RecBuff;
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blockOut <= RecBuff.Words;
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AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
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AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
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writeb <= '1';
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writeb <= '1';
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flag <= '1';
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stateram <= ramflush;
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stateram <= ramflush;
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end if;
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end if;
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when ramwait =>
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if hi = '1' then
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stateram <= ramwait1;
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end if;
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end if;
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when ramwait1 =>
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when ramwait1 =>
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writec <= '0';
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if del /= 15 and enableram = '1' then
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if del /= 15 and enableram = '1' then
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if toflush = AddressInh( toflush'range) then -- inserted, tagline could match flushing tagline !!!!
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if toflush = AddressInh( toflush'range) then -- inserted, tagline could match flushing tagline !!!!
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tagBuff( del).tagvalid <= '0';
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tagBuff( del).tagvalid <= '0';
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tagBuff( del).cacheValid <= '0';
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tagBuff( del).cacheValid <= '0';
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tagBuff( del).tag <= ( others => '0');
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tagBuff( del).tag <= ( others => '0');
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| Line 502... |
Line 505... |
cacheIn.FiFoAddr <= newFiFoAddr;
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cacheIn.FiFoAddr <= newFiFoAddr;
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cacheIn.Am <= newAm;
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cacheIn.Am <= newAm;
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getf <= '0';
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getf <= '0';
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writec <= '1';
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writec <= '1';
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doneh <= '1';
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if hi = '1' then
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stateram <= ramwait1;
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elsif acc = '1' then
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doneh <= '1';
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stateram <= ramupdate3;
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stateram <= ramupdate3;
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end if;
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when ramupdate3 =>
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when ramupdate3 =>
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hi := '0';
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hi := '0';
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acc := '0';
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acc := '0';
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en := '0';
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en := '0';
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writec <= '0';
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writec <= '0';
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| Line 532... |
Line 539... |
end loop;
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end loop;
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stateram <= ramflush1;
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stateram <= ramflush1;
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when ramflush1 =>
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when ramflush1 =>
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if writesh = '0' then
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if writesh = '0' then
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if del /= 15 and hi = '1' then
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if flag = '1' then
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hi := '0';
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stateram <= ramwait;
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else
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tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
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tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
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tagBuff( elim).tagValid <= '1';
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tagBuff( elim).tagValid <= '1';
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flag <= '0';
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if IOCodeh = "111" and ldCachedWords = 0 then
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if IOCodeh = "111" and ldCachedWords = 0 then
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stateram <= ramupdate2;
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stateram <= ramupdate2;
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else
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else
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readb <= '1';
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readb <= '1';
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AddressOut <= AddressInh( AddressOut'range);
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AddressOut <= AddressInh( AddressOut'range);
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stateram <= ramread;
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stateram <= ramread;
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end if;
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end if;
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elsif isfull = '1' then
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hi := '0';
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stateram <= ramstart;
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elsif acc = '1' then
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doneh <= '1';
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stateram <= ramupdate3;
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end if;
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end if;
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end if;
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end if;
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end case;
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end case;
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accinterrupt <= hi;
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accinterrupt <= hi;
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| Line 674... |
Line 685... |
A1Inaddr <= RecBuff.FiFoAddr;
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A1Inaddr <= RecBuff.FiFoAddr;
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removeA1 <= '1';
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removeA1 <= '1';
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statequeue <= queuewaitAm1;
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statequeue <= queuewaitAm1;
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end if;
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end if;
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elsif free /= 15 then
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elsif free /= 15 then
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if fullA1 = '1' or (emptyf = '1' and emptyA1 = '0' and serviced = '0') then
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if fullA1 = '1' or (isfull = '1' and emptyA1 = '0' and serviced = '0') then
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-- remove last entry from A1
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-- remove last entry from A1
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if A1Out.valid = '1' then
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if A1Out.valid = '1' then
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del <= to_integer( A1Out.way);
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del <= to_integer( A1Out.way);
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toFlush <= A1Out.word;
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toFlush <= A1Out.word;
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getA1 <= '1';
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getA1 <= '1';
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hi := '1';
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hi := '1';
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serviced <= '1';
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serviced <= '1';
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statequeue <= queuewait;
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statequeue <= queuewait;
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end if;
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end if;
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elsif fullAm = '1' and emptyf = '1' and serviced = '0' then
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elsif emptyAm = '0' and isfull = '1' and serviced = '0' then
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-- remove last entry from Am
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-- remove last entry from Am
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if AmOut.valid = '1' then
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if AmOut.valid = '1' then
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del <= to_integer( AmOut.way);
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del <= to_integer( AmOut.way);
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toFlush <= AmOut.word;
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toFlush <= AmOut.word;
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getAm <= '1';
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getAm <= '1';
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