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https://opencores.org/ocsvn/mytwoqcache/mytwoqcache/trunk
[/] [mytwoqcache/] [trunk/] [2QCache.vhd] - Diff between revs 24 and 25
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| Rev 24 |
Rev 25 |
| Line 411... |
Line 411... |
end if;
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end if;
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end if;
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end if;
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when ramupdate =>
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when ramupdate =>
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stateram <= ramupdate1;
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stateram <= ramupdate1;
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when ramupdate1 =>
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when ramupdate1 =>
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en := '1';
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if found /= 15 then
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cacheIn <= cacheOut;
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cacheIn <= cacheOut;
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blockOut <= cacheOut.Words;
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blockOut <= cacheOut.Words;
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RecBuff <= cacheOut;
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RecBuff <= cacheOut;
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en := '1';
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if found /= 15 then
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stateram <= ramupdate2;
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stateram <= ramupdate2;
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elsif free /= 15 then
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elsif free /= 15 then
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tagBuff( free).cacheAddr <= FreeOut;
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tagBuff( free).cacheAddr <= FreeOut;
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tagBuff( free).cacheValid <= '1';
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tagBuff( free).cacheValid <= '1';
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tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
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tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
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| Line 431... |
Line 431... |
readb <= '1';
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readb <= '1';
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AddressOut <= AddressInh( AddressOut'range);
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AddressOut <= AddressInh( AddressOut'range);
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stateram <= ramread;
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stateram <= ramread;
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end if;
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end if;
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else
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else
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cacheIn <= cacheOut;
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blockOut <= cacheOut.Words;
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RecBuff <= cacheOut;
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AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
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AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
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writeb <= '1';
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writeb <= '1';
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flag <= '1';
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flag <= '1';
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stateram <= ramflush;
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stateram <= ramflush;
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end if;
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end if;
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