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[/] [mytwoqcache/] [trunk/] [2QCache.vhd] - Diff between revs 24 and 25

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Rev 24 Rev 25
Line 411... Line 411...
                                end if;
                                end if;
                         end if;
                         end if;
                  when ramupdate =>
                  when ramupdate =>
                    stateram <= ramupdate1;
                    stateram <= ramupdate1;
                  when ramupdate1 =>
                  when ramupdate1 =>
 
                         en := '1';
 
                         if found /= 15 then
                     cacheIn <= cacheOut;
                     cacheIn <= cacheOut;
                         blockOut <= cacheOut.Words;
                         blockOut <= cacheOut.Words;
                         RecBuff <= cacheOut;
                         RecBuff <= cacheOut;
                         en := '1';
 
                         if found /= 15 then
 
                           stateram <= ramupdate2;
                           stateram <= ramupdate2;
                         elsif free /= 15 then
                         elsif free /= 15 then
                           tagBuff( free).cacheAddr <= FreeOut;
                           tagBuff( free).cacheAddr <= FreeOut;
                           tagBuff( free).cacheValid <= '1';
                           tagBuff( free).cacheValid <= '1';
                           tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
                           tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
Line 431... Line 431...
                             readb <= '1';
                             readb <= '1';
                             AddressOut <= AddressInh( AddressOut'range);
                             AddressOut <= AddressInh( AddressOut'range);
                             stateram <= ramread;
                             stateram <= ramread;
                           end if;
                           end if;
                         else
                         else
 
                       cacheIn <= cacheOut;
 
                           blockOut <= cacheOut.Words;
 
                           RecBuff <= cacheOut;
                           AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
                           AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
                       writeb <= '1';
                       writeb <= '1';
                           flag <= '1';
                           flag <= '1';
                           stateram <= ramflush;
                           stateram <= ramflush;
                         end if;
                         end if;

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