| Line 1... |
Line 1... |
[](https://github.com/stnolting/neorv32)
|
[](https://github.com/stnolting/neorv32)
|
|
|
# The NEORV32 RISC-V Processor
|
# The NEORV32 RISC-V Processor
|
|
|
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[](https://stnolting.github.io/neorv32)
|
[](https://stnolting.github.io/neorv32)
|
| Line 10... |
Line 10... |
[](https://gitter.im/neorv32/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
|
[](https://gitter.im/neorv32/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
|
|
|
1. [Overview](#1-Overview)
|
1. [Overview](#1-Overview)
|
* [Key Features](#Project-Key-Features)
|
* [Key Features](#Project-Key-Features)
|
* [Status](#status)
|
* [Status](#status)
|
2. [Processor/SoC Features](#2-NEORV32-Processor-Features)
|
2. [Features](#2-Features)
|
* [FPGA Implementation Results](#FPGA-Implementation-Results---Processor)
|
3. [FPGA Implementation Results](#3-FPGA-Implementation-Results)
|
3. [CPU Features](#3-NEORV32-CPU-Features)
|
4. [Performance](#4-Performance)
|
* [Available ISA Extensions](#Available-ISA-Extensions)
|
5. [Software Framework & Tooling](#5-Software-Framework-and-Tooling)
|
* [FPGA Implementation Results](#FPGA-Implementation-Results---CPU)
|
6. [**Getting Started**](#6-Getting-Started) :rocket:
|
* [Performance](#Performance)
|
|
4. [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
|
|
5. [**Getting Started**](#5-Getting-Started) :rocket:
|
|
|
|
|
|
|
|
## 1. Overview
|
## 1. Overview
|
|
|
| Line 61... |
Line 58... |
|
|
### Project Key Features
|
### Project Key Features
|
|
|
- [x] all-in-one package: **CPU** plus **SoC** plus **Software Framework & Tooling**
|
- [x] all-in-one package: **CPU** plus **SoC** plus **Software Framework & Tooling**
|
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
|
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
|
|
- [x] highly [extensible hardware](https://stnolting.github.io/neorv32/ug/#_comparative_summary) - on CPU, SoC and system level
|
- [x] be as small as possible while being as RISC-V-compliant as possible
|
- [x] be as small as possible while being as RISC-V-compliant as possible
|
- [x] from zero to `printf("hello world!");` - completely open source and documented
|
- [x] from zero to `printf("hello world!");` - completely open source and documented
|
- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
|
- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
|
|
|
|
|
| Line 72... |
Line 70... |
|
|
[](https://github.com/stnolting/neorv32/releases)
|
[](https://github.com/stnolting/neorv32/releases)
|
[](https://stnolting.github.io/neorv32)
|
[](https://stnolting.github.io/neorv32)
|
\
|
\
|
[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
|
[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
|
[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
|
[](https://github.com/stnolting/neorv32-verif/actions?query=workflow%3Ariscv-arch-test)
|
[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
|
[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
|
|
|
|
The NEORV32 is fully operational.
|
|
The processor passes the official RISC-V architecture tests, which are checked by the
|
|
[neorv32-verif](https://github.com/stnolting/neorv32-verif) repository. It can successfully run _any_ C program
|
|
(for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example) folder) including CoreMark
|
|
and can be synthesized for _any_ target technology - tested on Intel, Xilinx and Lattice FPGAs.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
## 2. NEORV32 Processor Features
|
|
|
|
The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. It is highly configurable
|
## 2. Features
|
via generics to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
|
|
|
The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU.
|
|
By using generics the design is highly configurable and allows a flexible customization to tailor the
|
|
setup according to your needs. The following list shows all available SoC module. Note that all those
|
|
modules are _optional_.
|
|
|
|
**CPU**
|
|
|
|
* 32-bit little-endian RISC-V single-core, pipelined/multi-cycle Von-Neumann architecture
|
|
* configurable ISA extensions
|
|
* `RV32`
|
|
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
|
|
[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
|
|
[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
|
|
[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)]
|
|
[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
|
|
[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
|
|
[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
|
|
[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
|
|
[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
|
|
[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
|
|
[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
|
|
[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
|
|
[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
|
|
[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
|
|
[[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_custom_instructions_extension_cfu)]
|
|
[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
|
|
[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]
|
|
* compatible to subsets of the
|
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf)
|
|
and the *Privileged Architecture Specification* [(Version 1.12)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf).
|
|
* `machine` and `user` modes
|
|
* implements _all_ standard RISC-V exceptions/interrupts (including MTI, MEI & MSI)
|
|
* 16-fast interrupt requests as NEORV32-specific extensions
|
|
|
**Memory**
|
**Memory**
|
|
|
* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
|
* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
|
[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
|
[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
|
| Line 111... |
Line 147... |
|
|
**SoC Connectivity**
|
**SoC Connectivity**
|
|
|
* 32-bit external bus interface, Wishbone b4 compatible
|
* 32-bit external bus interface, Wishbone b4 compatible
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
|
* [wrapper](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite host interface
|
* [wrappers](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration) for AXI4-Lite and Avalon-MM host interfaces
|
* [wrapper](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM host interface
|
|
* 32-bit stream link interface with up to 8 independent RX and TX links
|
* 32-bit stream link interface with up to 8 independent RX and TX links
|
([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
|
([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink)) - AXI4-Stream compatible
|
* AXI4-Stream compatible
|
* external interrupts controller with up to 32 channels
|
* external interrupt controller with up to 32 channels
|
|
([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
|
|
**Advanced**
|
**Advanced**
|
|
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - compliant to
|
|
the "Minimal RISC-V Debug Specification Version 0.13.2" and compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**
|
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* execute in place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to directly execute code from SPI flash
|
* execute in place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to directly execute code from SPI flash
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
for tightly-coupled custom accelerators and interfaces
|
for tightly-coupled custom accelerators and interfaces
|
* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu)) for up to 1024
|
* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu)) for up to 1024
|
_custom RISC-V instructions_
|
_custom RISC-V instructions_
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
**Debugging**
|
|
|
|
|
### FPGA Implementation Results - Processor
|
|
|
|
The hardware resources used by a specific processor setup is defined by the implemented CPU extensions,
|
|
the configuration of the peripheral modules and some "glue logic".
|
|
Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules)
|
|
of the online datasheet shows the resource utilization of each optional processor module to allow an
|
|
estimation of the actual setup's hardware requirements.
|
|
|
|
:bulb: The [`neorv32-setups`](https://github.com/stnolting/neorv32-setups) repository provides exemplary FPGA
|
|
setups targeting various FPGA boards and toolchains. The latest bitstreams and utilization reports for those setups
|
|
can be found in the assets of the [Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via standard JTAG interface
|
|
* compliant to the "Minimal RISC-V Debug Specification Version 0.13.2"
|
|
* compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**
|
|
|
## 3. NEORV32 CPU Features
|
|
|
|
The NEORV32 CPU implements the RISC-V 32-bit `rv32i` ISA with optional extensions (see below). It is compatible to subsets of the
|
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf)
|
|
and the *Privileged Architecture Specification* [(Version 1.12)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf).
|
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test).
|
|
|
|
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
|
|
However, the CPU's_front end (instruction fetch) and back end (instruction execution) can work independently to increase performance.
|
|
Currently, two privilege levels "machine-mode" and optional "user-mode" are supported. The CPU implements all three standard RISC-V machine
|
|
interrupts (MTI, MEI, MSI) plus 16 _fast interrupt requests_ as custom extensions.
|
|
It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
|
|
instruction, breakpoint, environment calls).
|
|
|
|
:books: In-depth detailed information regarding the CPU can be found in the
|
|
[_Data Sheet: NEORV32 Central Processing Unit_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
|
|
|
|
:warning: The `B`, `Zfinx` and `Zmmul` RISC-V ISA extensions are frozen and officially ratified but there is no
|
### Available ISA Extensions
|
upstream gcc support yet (will be available with GCC12). To circumvent this, the NEORV32 software framework provides
|
|
_intrinsic libraries_ for the `B` and `Zfinx` extensions.
|
The following _optional_ RISC-V-compatible and NEORV32-specific ISA extensions are available (linked to the according
|
|
documentation section):
|
|
|
|
**RV32
|
|
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
|
|
[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
|
|
[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
|
|
[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)]
|
|
[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
|
|
[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
|
|
[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
|
|
[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
|
|
[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
|
|
[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
|
|
[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
|
|
[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
|
|
[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
|
|
[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
|
|
[[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_custom_instructions_extension_cfu)]
|
|
[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
|
|
[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
|
|
|
|
:warning: The `B`, `Zfinx` and `Zmmul` RISC-V are frozen and officially ratified but there is no
|
|
upstream gcc support yet. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for the
|
|
`B` and `Zfinx` extensions.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### FPGA Implementation Results - CPU
|
## 3. FPGA Implementation Results
|
|
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV E** `EP4CE22F17C6` FPGA
|
Implementation results for exemplary **CPU-only** configuration generated for an Intel Cyclone IV E `EP4CE22F17C6` FPGA
|
using **Intel Quartus Prime Lite 21.1** (no timing constrains, _balanced optimization_, f_max from _Slow 1200mV 0C Model_).
|
using Intel Quartus Prime Lite 21.1 (no timing constrains, _balanced optimization_, f_max from _Slow 1200mV 0C Model_).
|
|
|
| CPU Configuration (version [1.6.8.3](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
|
| CPU Configuration (version [1.6.9.8](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
|
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
|
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
|
| `rv32i_Zicsr` | 1425 | 673 | 1024 | 0 | 118 MHz |
|
| `rv32i_Zicsr` | 1328 | 678 | 1024 | 0 | 128 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1778 | 803 | 1024 | 0 | 118 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1614 | 808 | 1024 | 0 | 128 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2453 | 994 | 1024 | 0 | 118 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2338 | 992 | 1024 | 0 | 128 MHz |
|
|
|
:bulb: An incremental list of the CPUs ISA extension's hardware utilization can found in the
|
:bulb: An incremental list of the CPUs ISA extension's hardware utilization can found in the
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
|
|
|
The hardware resources used by a specific **full-processor** setup is defined by the implemented CPU extensions,
|
|
the configuration of the peripheral modules and some "glue logic".
|
|
Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules)
|
|
of the online datasheet shows the resource utilization of each optional processor module to allow an
|
|
estimation of the actual setup's hardware requirements.
|
|
|
|
:bulb: The [`neorv32-setups`](https://github.com/stnolting/neorv32-setups) repository provides exemplary FPGA
|
|
setups targeting various FPGA boards and toolchains. The latest bitstreams and utilization reports for those setups
|
|
can be found in the assets of the [Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).
|
|
|
|
:bulb: The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area
|
|
or minimal power consumption:
|
|
[UG: Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration)
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### Performance
|
## 4. Performance
|
|
|
The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
|
The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
available CPU extensions.
|
available CPU extensions.
|
|
|
| Line 238... |
Line 230... |
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## 4. Software Framework and Tooling
|
## 5. Software Framework and Tooling
|
|
|
* [core libraries](https://github.com/stnolting/neorv32/tree/main/sw/lib) for high-level usage of the provided functions and peripherals
|
* [core libraries](https://github.com/stnolting/neorv32/tree/main/sw/lib) for high-level usage of the provided functions and peripherals
|
* application compilation based on GNU makefiles
|
* application compilation based on GNU makefiles
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* [SVD file](https://github.com/stnolting/neorv32/tree/main/sw/svd) for advanced debugging and IDE integration
|
* [SVD file](https://github.com/stnolting/neorv32/tree/main/sw/svd) for advanced debugging and IDE integration
|
| Line 262... |
Line 254... |
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## 5. Getting Started
|
## 6. Getting Started
|
|
|
This overview provides some *quick links* to the most important sections of the
|
This overview provides some *quick links* to the most important sections of the
|
[online Data Sheet](https://stnolting.github.io/neorv32) and the
|
[online Data Sheet](https://stnolting.github.io/neorv32) and the
|
[online User Guide](https://stnolting.github.io/neorv32/ug).
|
[online User Guide](https://stnolting.github.io/neorv32/ug).
|
|
|
| Line 314... |
Line 306... |
[](https://github.com/stnolting/neorv32/blob/main/LICENSE)
|
[](https://github.com/stnolting/neorv32/blob/main/LICENSE)
|
[](https://doi.org/10.5281/zenodo.5018888)
|
[](https://doi.org/10.5281/zenodo.5018888)
|
|
|
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ...
|
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ...
|
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
* [Impressum](https://github.com/stnolting/neorv32/blob/main/docs/impressum.md) - imprint
|
|
|
|
This is an open-source project that is free of charge. Use this project in any way you like
|
This is an open-source project that is free of charge. Use this project in any way you like
|
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/main/LICENSE)).
|
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/main/LICENSE)).
|
Please quote it appropriately. :+1:
|
Please quote it appropriately. :+1:
|
|
|
