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# [The NEORV32 Processor](https://github.com/stnolting/neorv32)
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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V-compliant)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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## Introduction
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## Introduction
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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The NEORV32 is a customizable full-scale mikrocontroller-like processor system based on a [RISC-V-compliant](https://github.com/stnolting/neorv32_riscv_compliance)
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`M`, `C`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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`rv32i` CPU with optional `E`, `C`, `M`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12-draft**.
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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The NEORV32 is intended as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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Its top entity can be directly synthesized for any FPGA without modifications and provides a full-scale RISC-V based microcontroller.
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled and configured via VHDL generics.
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled and configured via VHDL generics.
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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provided functions and peripherals, application makefiles and example programs. All software source files
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provided functions and peripherals, application makefiles, a runtime environment and several example programs. All software source files
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provide a doxygen-based documentary. The deployed doxygen-based software documentation can be found on the
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provide a doxygen-based [documentary](https://stnolting.github.io/neorv32/files.html).
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project's [Github pages](https://stnolting.github.io/neorv32/files.html).
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
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it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain)
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it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain)
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by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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by yourself, you can also download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Design Principles
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### Design Principles
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project | Status | Misc |
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| Project component | CI status | Note |
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|:--------------------------------------------------------------------------------|:-------|:---------|
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|:--------------------------------------------------------------------------------|:----------|:---------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) |
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### Limitations to be fixed
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### Limitations to be fixed
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* No exception is triggered in `E`-mode when using registers above `x15` yet
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* No exception is triggered in `E`-mode when using registers above `x15` yet
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* `misa` CSR is read-only; no dynamic enabling/disabling of implemented CPU extensions during runtime
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### To-Do / Wish List
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### To-Do / Wish List
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- Synthesis results for more platforms
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- Synthesis results for more platforms
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## Features
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## Features
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### Processor Features
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### Processor Features
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available [@Github pages](https://stnolting.github.io/neorv32/files.html)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Small hardware footprint and high operating frequency
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- Highly customizable processor configuration
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- Highly customizable processor configuration
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- _Optional_ GARO-based true random number generator (TRNG)
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- _Optional_ GARO-based true random number generator (TRNG)
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- _Optional_ core-local interrupt controller with 8 channels (CLIC)
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- _Optional_ core-local interrupt controller with 8 channels (CLIC)
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- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output)
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### CPU Features
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### CPU Features
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The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the
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[official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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**General**:
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* No hardware support of unaligned accesses - they will trigger and exception
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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**RV32I base instruction set** (`I` extension):
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* System instructions: `ECALL` `EBREAK` `FENCE`
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* System instructions: `ECALL` `EBREAK` `FENCE`
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**Privileged architecture / CSR access** (`Zicsr` extension):
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Supported exceptions and interrupts:
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Misaligned instruction address
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* Instruction access fault
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* Instruction access fault
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* Illegal instruction
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* Illegal instruction
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* Load address misaligned
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* Load address misaligned
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* Load access fault
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* Load access fault
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* Store address misaligned
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* Store address misaligned
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* Store access fault
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* Store access fault
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* Environment call from M-mode (via `ecall` instruction)
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* Environment call from M-mode (via `ecall` instruction)
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* Machine software instrrupt `msi`
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* Machine software interrupt `msi`
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* Machine timer interrupt `mti` (via MTIME unit)
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* Machine timer interrupt `mti` (via MTIME unit)
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* Machine external interrupt `mei` (via CLIC unit)
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* Machine external interrupt `mei` (via CLIC unit)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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* System instructions: `FENCE.I`
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* System instructions: `FENCE.I`
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**General**:
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* No hardware support of unaligned accesses - they will trigger and exception
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
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More information including a detailed list of the available CSRs can be found in
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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## FPGA Implementation Results
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## FPGA Implementation Results
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the processor's generics is assumed. No constraints were used.
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of the processor's generics is assumed. No constraints were used.
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Results generated for hardware version: `1.0.0.0`
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### CPU
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### CPU
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Results generated for hardware version: `1.0.0.0`
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
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|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
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| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz |
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| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz |
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| `rv32i` + `Zicsr` | 1721 | 868 | 2048 | 0 (0%) | 104 MHz |
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| `rv32i` + `Zicsr` | 1721 | 868 | 2048 | 0 (0%) | 104 MHz |
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| `rv32im` + `Zicsr` | 2298 | 1115 | 2048 | 0 (0%) | 103 MHz |
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| `rv32im` + `Zicsr` | 2298 | 1115 | 2048 | 0 (0%) | 103 MHz |
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| `rv32imc` + `Zicsr` | 2557 | 1138 | 2048 | 0 (0%) | 103 MHz |
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| `rv32imc` + `Zicsr` | 2557 | 1138 | 2048 | 0 (0%) | 103 MHz |
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| `rv32emc` + `Zicsr` | 2342 | 1005 | 1024 | 0 (0%) | 100 MHz |
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| `rv32emc` + `Zicsr` | 2342 | 1005 | 1024 | 0 (0%) | 100 MHz |
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### Processor-Internal Peripherals and Memories
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### Processor-Internal Peripherals and Memories
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Results generated for hardware version: `1.0.5.0`
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
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| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 |
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| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| MTIME | Machine system timer | 270 | 167 | 0 | 0 |
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| MTIME | Machine system timer | 269 | 166 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 |
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| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 |
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| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 |
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| TRNG | True random number generator | 104 | 93 | 0 | 0 |
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| TRNG | True random number generator | 104 | 93 | 0 | 0 |
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| TWI | Two-wire interface | 78 | 44 | 0 | 0 |
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| TWI | Two-wire interface | 78 | 44 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 |
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| WDT | Watchdog timer | 57 | 45 | 0 | 0 |
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| WDT | Watchdog timer | 57 | 45 | 0 | 0 |
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### CPU + Peripheral
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The following table shows the implementation results for an _Intel Cyclone IV EP4CE22F17C6N_ FPGA.
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The design was synthesized using Intel Quartus Prime Lite 19.1 (“balanced implementation”).
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IMEM uses 16kB and DMEM uses 8kB memory space.
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| CPU Configuration | LEs | REGs | DSPs | Memory Bits | f_max |
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|:--------------------|:----------:|:---------:|:------:|:------------:|:-------:|
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| `rv32imc` + `Zicsr` | 3724 (17%) | 1899 (9%) | 0 (0%) | 231424 (38%) | 103 MHz |
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### Exemplary FPGA Setups
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### Lattice iCE40 UltraPlus 5k
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Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
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all CPU extensions (`rv32imc` + `Zicsr` + `Zifencei`, no `E` extension), no external memory interface and only internal
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The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
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instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup top entity connects most of the
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The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
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processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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instruction and data memories (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the
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to FPGA pins - except for the Wishbone bus and the external interrupt signals.
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[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
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Results generated for hardware version: `1.0.1.1`
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Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
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is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
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| Vendor | FPGA | Board | Toolchain | Impl. strategy | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
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|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|------------:|
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| CPU Configuration | LUTs | REGs | DSPs | SPRAM | EBR | f |
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| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | 3841 (17%) | 1866 (8%) | 0 (0%) | 231424 (38%) | - | - | 103 MHz |
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|:--------------------|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | default | 5014 (95%) | 1952 (37%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 20.25 MHz |
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| `rv32imc` + `Zicsr` | 4985 (94%) | 1982 (38%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | 2312 (11%) | 1924 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz |
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**Notes**
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
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The FPGA-specific memory components can be found in the [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are `f_max` results from the place and route timing reports.
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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bootloader to store and automatically boot an application program after reset (both tested successfully).
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
### CoreMark Benchmark
|
|
|
| Line 243... |
Line 249... |
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock
|
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CPU extensions: `rv32i` or `rv32im` or `rv32imc`
|
CPU extensions: `rv32i` or `rv32im` or `rv32imc`
|
Used peripherals: MTIME for time measurement, UART for printing the results
|
Used peripherals: UART for printing the results
|
~~~
|
~~~
|
|
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
|
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
|
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
|
| `rv32i` | `-Os` | 18 044 bytes | 21.98 | 0.21 |
|
| `rv32i` | `-Os` | 18 044 bytes | 21.98 | 0.21 |
|
| Line 258... |
Line 264... |
| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
|
| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
|
|
|
|
|
### Instruction Cycles
|
### Instruction Cycles
|
|
|
The NEORV32 CPU is based on two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
CPU extensions.
|
CPU extensions.
|
|
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
| Line 409... |
Line 415... |
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
|
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
|
|
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
|
|
|
|
### Dowload the NEORV32 Project and Create a Hardware Project
|
### Dowload the NEORV32 and Create a Hardware Project
|
|
|
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
|
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
|
`git` from the command line (suggested for easy project updates via `git pull`):
|
`git` from the command line (suggested for easy project updates via `git pull`):
|
|
|
$ git clone https://github.com/stnolting/neorv32.git
|
$ git clone https://github.com/stnolting/neorv32.git
|
|
|
Create a new HW project with your FPGA design tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
folder to this project and add them to a **new library** called `neorv32`.
|
folder to this project and add them to a **new library** called `neorv32`.
|
|
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
propagated:
|
This test setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
|
|
propagated (basically, its a FPGA "hello world" example):
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_test_setup is
|
entity neorv32_test_setup is
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
| Line 439... |
Line 446... |
uart_rxd_i : in std_ulogic := '0' -- UART receive data
|
uart_rxd_i : in std_ulogic := '0' -- UART receive data
|
);
|
);
|
end neorv32_test_setup;
|
end neorv32_test_setup;
|
```
|
```
|
|
|
This test setup is intended as quick and easy "hello world" test setup to get into the NEORV32.
|
|
|
|
|
|
### Compiling and Uploading One of the Example Projects
|
### Compiling and Uploading One of the Example Projects
|
|
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
|
`sw/example/blink_led` and run:
|
`sw/example/blink_led` and run:
|
|
|
neorv32/sw/example/blink_led$ make check
|
neorv32/sw/example/blink_led$ make check
|
|
|
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
| Line 511... |
Line 516... |
If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
|
If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
|
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
|
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
|
|
|
|
|
|
|
## Citation
|
## Legal
|
|
|
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
|
|
|
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
|
|
|
|
This is project is released under the BSD 3-Clause license. No copyright infringement intended.
|
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
|
|
|
#### Citation
|
|
|
## Legal
|
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
|
|
|
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
Other implied/used projects might have different licensing - see their documentation to get more information.
|
|
|
|
#### BSD 3-Clause License
|
#### BSD 3-Clause License
|
|
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
|
|
| Line 562... |
Line 565... |
when the links were placed, no infringements of the law were recognisable to us. As soon
|
when the links were placed, no infringements of the law were recognisable to us. As soon
|
as an infringement of the law becomes known to us, we will immediately remove the
|
as an infringement of the law becomes known to us, we will immediately remove the
|
link in question.
|
link in question.
|
|
|
|
|
#### Propretary Notice
|
#### Proprietary Notice
|
|
|
"Windows" is a trademark of Microsoft Corporation.
|
"Windows" is a trademark of Microsoft Corporation.
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
|
|
"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation.
|
"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
|
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
|
|
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
|
#### Misc
|
## Acknowledgement
|
|
|
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
|
|
|
[](https://travis-ci.com/stnolting/neorv32)
|
[](https://travis-ci.com/stnolting/neorv32)
|
|
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
|
|
|
|
|
|
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
|
|
|
\
|
|
|
Made with :coffee: in Hannover, Germany.
|
Made with :coffee: in Hannover, Germany.
|
