| Line 73... |
Line 73... |
* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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### To-Do / Wish List
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### To-Do / Wish List
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|
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- Option to use DSPs for multiplications in `M` extensions (would be so much faster)
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- Add instructions how to use the NEORV32 CPU without the processor surroundings
|
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- Add AXI / AXI-Lite bridges
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Synthesis results for more platforms
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- Synthesis results for more platforms
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- Port Dhrystone benchmark
|
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- Implement atomic operations (`A` extension)
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- Implement co-processor for single-precision floating-point operations (`F` extension)
|
|
- Implement user mode (`U` extension)
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- Implement user mode (`U` extension)
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- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
|
- Port Dhrystone benchmark
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- Make a 64-bit branch
|
- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
|
|
- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
|
|
- Make a 64-bit branch someday
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## Features
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## Features
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| Line 221... |
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Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
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Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
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no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
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no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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to FPGA pins - except for the Wishbone bus and the interrupt signals.
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to FPGA pins - except for the Wishbone bus and the interrupt signals.
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Results generated for hardware version: `1.2.0.0`
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Results generated for hardware version: `1.2.0.6`
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| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|------------:|
|
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|-------------:|
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 4066 (18%) | 1877 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 4035 (18%) | 1860 (8%) | 0 (0%) | 231424 (38%) | - | - | 101 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 5017 (95%) | 1717 (32%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 20.25 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 5001 (95%) | 1694 (32%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 22.5 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2494 (12%) | 1930 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2509 (12%) | 1914 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz |
|
|
|
**Notes**
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**Notes**
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
| Line 481... |
Line 482... |
<< NEORV32 Bootloader >>
|
<< NEORV32 Bootloader >>
|
|
|
BLDV: Jul 6 2020
|
BLDV: Jul 6 2020
|
HWV: 1.0.1.0
|
HWV: 1.0.1.0
|
CLK: 0x0134FD90 Hz
|
CLK: 0x0134FD90 Hz
|
MHID: 0x0001CE40
|
USER: 0x0001CE40
|
MISA: 0x42801104
|
MISA: 0x42801104
|
CONF: 0x03FF0035
|
CONF: 0x03FF0035
|
IMEM: 0x00010000 bytes @ 0x00000000
|
IMEM: 0x00010000 bytes @ 0x00000000
|
DMEM: 0x00010000 bytes @ 0x80000000
|
DMEM: 0x00010000 bytes @ 0x80000000
|
|
|
| Line 580... |
Line 581... |
|
|
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
|
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
|
|
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
|
## Acknowledgement
|
## Acknowledgement
|
|
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
|
