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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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### To-Do / Wish List
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### To-Do / Wish List
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- Add AXI / AXI-Lite bridges
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- Add AXI(-Lite) bridges
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Synthesis results for more platforms
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- Synthesis results for more platforms
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- Port Dhrystone benchmark
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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* Machine software interrupt `msi` (via external signal)
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* Machine software interrupt `msi` (via external signal)
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* Machine external interrupt `mei` (via external signal)
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* Machine external interrupt `mei` (via external signal)
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* Four fast interrupt requests (custom extension)
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* Four fast interrupt requests (custom extension)
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode) + `U-Mode` (User mode)
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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* System instructions: `FENCEI`
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* System instructions: `FENCEI`
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**Physical memory protection** (`PMP`, requires `Zicsr` extension):
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**Physical memory protection** (`PMP`, requires `Zicsr` extension):
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The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
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Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
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(except for the TWI signals, which are of type *std_logic*).
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(except for the TWI signals, which are of type *std_logic*).
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The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
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The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
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All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
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Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
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Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
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Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
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Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Memory configuration: Instruction memory --
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Bus Interface --
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-- Bus Interface --
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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