| Line 61... |
Line 61... |
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* From zero to main(): Completely open source and documented.
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* From zero to main(): Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Easy to use – working out of the box.
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* Easy to use – working out of the box.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Be as small as possible – but with a reasonable size-speed tradeoff.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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### Status
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| Line 84... |
Line 85... |
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `mcause` CSR is read-only
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* `mcause` CSR is read-only
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The physical memory protection (**PMP**) only supports `NAPOT` mode and only up to 8 regions
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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### Custom CPU Extensions
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### Custom CPU Extensions
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|
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The custom extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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The custom extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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| Line 192... |
Line 193... |
* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
|
**Privileged architecture / FENCE.I** (`Zifencei` extension):
|
* System instructions: `FENCE.I`
|
* System instructions: `FENCE.I`
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|
|
**Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
* Additional machine CSRs: `pmpcfgx` `pmpaddrx`
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* Additional machine CSRs: `pmpcfgx` `pmpaddrx`
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## FPGA Implementation Results
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## FPGA Implementation Results
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|
|
| Line 278... |
Line 279... |
Compiler: RISCV32-GCC 10.1.0
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Compiler: RISCV32-GCC 10.1.0
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Peripherals: UART for printing the results
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Peripherals: UART for printing the results
|
~~~
|
~~~
|
|
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
|:---------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
|:----------|:---------------:|:------------:|:--------------:|:-------------:|
|
| `rv32i` + `Zicsr` + `Zifencei` | 21 600 bytes | `-O2` | 27.02 | 0.2702 |
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| `rv32i` | 21 600 bytes | `-O2` | 27.02 | 0.2702 |
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| `rv32im` + `Zicsr` + `Zifencei` | 20 976 bytes | `-O2` | 57.14 | 0.5714 |
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| `rv32im` | 20 976 bytes | `-O2` | 57.14 | 0.5714 |
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| `rv32imc` + `Zicsr` + `Zifencei` | 16 348 bytes | `-O2` | 57.14 | 0.5714 |
|
| `rv32imc` | 16 348 bytes | `-O2` | 57.14 | 0.5714 |
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|
|
|
|
### Instruction Cycles
|
### Instruction Cycles
|
|
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
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| Line 302... |
Line 303... |
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`.
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`.
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
|:---------------------------------|----------------------:|----------------------:|:-----------:|
|
|:----------|----------------------:|----------------------:|:-----------:|
|
| `rv32i` + `Zicsr` + `Zifencei` | 7 433 933 906 | 1 494 298 800 | 4.97 |
|
| `rv32i` | 7 433 933 906 | 1 494 298 800 | 4.97 |
|
| `rv32im` + `Zicsr` + `Zifencei` | 3 589 861 906 | 628 281 454 | 5.71 |
|
| `rv32im` | 3 589 861 906 | 628 281 454 | 5.71 |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 3 587 131 226 | 628 282 016 | 5.70 |
|
| `rv32imc` | 3 587 131 226 | 628 282 016 | 5.70 |
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|
|
|
|
|
|
## Top Entities
|
## Top Entities
|
|
|
| Line 662... |
Line 663... |
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
|
"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
|
## Acknowledgement
|
## Acknowledgements
|
|
|
|
[](https://riscv.org/)
|
|
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
|
|
|
[](https://travis-ci.com/stnolting/neorv32)
|
[](https://travis-ci.com/stnolting/neorv32)
|
|
|
