Subversion Repositories neorv32

For more information take a look a the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).

For more information take a look a the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).

###  Key Features

###  Key Features

- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))

- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))

- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)

- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)

- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)

- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)

- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)

- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)

- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.

- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.

### To-Do / Wish List

### To-Do / Wish List

- Add AXI(-Lite) bridges

- Add AXI(-Lite) bridges

- Synthesis results for more platforms

- Synthesis results for more platforms

- Port Dhrystone benchmark

- Port Dhrystone benchmark

- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)

- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)

- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))

- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))

- Make a 64-bit branch someday

- Make a 64-bit branch someday

  * Reduced register file (only the 16 lowest registers)

  * Reduced register file (only the 16 lowest registers)

**Integer multiplication and division hardware** (`M` extension):

**Integer multiplication and division hardware** (`M` extension):

  * Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`

  * Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`

  * Division instructions: `DIV` `DIVU` `REM` `REMU`

  * Division instructions: `DIV` `DIVU` `REM` `REMU`

**Privileged architecture / CSR access** (`Zicsr` extension):

**Privileged architecture / CSR access** (`Zicsr` extension):

  * Privilege levels: `M-mode` (Machine mode)

  * Privilege levels: `M-mode` (Machine mode)

  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`

  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`

  * System instructions: `MRET` `WFI`

  * System instructions: `MRET` `WFI`

## FPGA Implementation Results

## FPGA Implementation Results

This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on

This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on

a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing

a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing

information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration

information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration

### CPU

### CPU

| CPU Configuration                | LEs        | FFs      | Memory bits | DSPs | f_max   |

| CPU Configuration                | LEs        | FFs      | Memory bits | DSPs | f_max   |

|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|

|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|

### Processor-Internal Peripherals and Memories

### Processor-Internal Peripherals and Memories

| Module    | Description                                     | LEs | FFs | Memory bits | DSPs |

| Module    | Description                                     | LEs | FFs | Memory bits | DSPs |

|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|

|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|

| BOOT ROM  | Bootloader ROM (4kB)                            |   4 |   1 |      32 768 |    0 |

| BOOT ROM  | Bootloader ROM (4kB)                            |   4 |   1 |      32 768 |    0 |

| BUSSWITCH | Mux for CPU I & D interfaces                    |  62 |   8 |           0 |    0 |

| BUSSWITCH | Mux for CPU I & D interfaces                    |  62 |   8 |           0 |    0 |

Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,

Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,

no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the

no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the

processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals

processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals

to FPGA pins - except for the Wishbone bus and the interrupt signals.

to FPGA pins - except for the Wishbone bus and the interrupt signals.

| Vendor  | FPGA                              | Board            | Toolchain               | Impl. strategy |CPU                               | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency      |

| Vendor  | FPGA                              | Board            | Toolchain               | Impl. strategy |CPU                               | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency      |

**Notes**

**Notes**

* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).

* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).

The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).

The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).

* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.

* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.

The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the

The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the

[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark

[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark

tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.

tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.

~~~

~~~

**Configuration**

**Configuration**

Hardware:    32kB IMEM, 16kB DMEM, 100MHz clock

Hardware:    32kB IMEM, 16kB DMEM, 100MHz clock

CoreMark:    2000 iterations, MEM_METHOD is MEM_STACK

CoreMark:    2000 iterations, MEM_METHOD is MEM_STACK

Compiler:    RISCV32-GCC 10.1.0

Compiler:    RISCV32-GCC 10.1.0

Peripherals: UART for printing the results

Peripherals: UART for printing the results

~~~

~~~

| CPU       | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |

| CPU       | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |

### Instruction Cycles

### Instruction Cycles

The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,

The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,

each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).

each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).

`M` extension use a bit-serial approach and require several cycles for completion.

`M` extension use a bit-serial approach and require several cycles for completion.

The following table shows the performance results for successfully running 2000 CoreMark

The following table shows the performance results for successfully running 2000 CoreMark

iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by

iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by

dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)

dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)

| CPU       | Required Clock Cycles | Executed Instructions | Average CPI |

| CPU       | Required Clock Cycles | Executed Instructions | Average CPI |

## Top Entities

## Top Entities

The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).

The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).

entity neorv32_top is

entity neorv32_top is

  generic (

  generic (

    -- General --

    -- General --

    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz

    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz

    BOOTLOADER_USE               : boolean := true;   -- implement processor-internal bootloader?

    BOOTLOADER_USE               : boolean := true;   -- implement processor-internal bootloader?

    USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code

    USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code

    -- RISC-V CPU Extensions --

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?

    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?

    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?

    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?

    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?

    -- Physical Memory Protection (PMP) --

    -- Physical Memory Protection (PMP) --

    PMP_USE                      : boolean := false;  -- implement PMP?

    PMP_USE                      : boolean := false;  -- implement PMP?

    PMP_NUM_REGIONS              : natural := 4;      -- number of regions (max 8)

    PMP_NUM_REGIONS              : natural := 4;      -- number of regions (max 8)

    PMP_GRANULARITY              : natural := 14;     -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k

    PMP_GRANULARITY              : natural := 14;     -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k

    -- Memory configuration: Instruction memory --

    -- Memory configuration: Instruction memory --

```vhdl

```vhdl

entity neorv32_cpu is

entity neorv32_cpu is

  generic (

  generic (

    -- General --

    -- General --

    HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id

    HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id

    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address

    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address

    -- RISC-V CPU Extensions --

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?

    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?

    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?

    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?

    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?

    -- Physical Memory Protection (PMP) --

    -- Physical Memory Protection (PMP) --

    PMP_USE                      : boolean := false; -- implement PMP?

    PMP_USE                      : boolean := false; -- implement PMP?

    PMP_NUM_REGIONS              : natural := 4;     -- number of regions (max 8)

    PMP_NUM_REGIONS              : natural := 4;     -- number of regions (max 8)

    PMP_GRANULARITY              : natural := 14;    -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k

    PMP_GRANULARITY              : natural := 14;    -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k

    -- Bus Interface --

    -- Bus Interface --