| Line 18... |
Line 18... |
|
|
|
|
|
|
## Introduction
|
## Introduction
|
|
|
The NEORV321 Processor is a customizable microcontroller-like system on chip (SoC) that is based
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
|
on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
|
on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
|
|
|
|
|
**[NEORV32 CPU](#CPU-Features)**
|
**[NEORV32 CPU](#CPU-Features)**
|
|
|
| Line 59... |
Line 59... |
The processor is intended to work "out of the box". Just synthesize the
|
The processor is intended to work "out of the box". Just synthesize the
|
[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
|
[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
|
with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
|
with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
|
download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
|
download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
|
|
|
For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
For more information take a look at the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
This project is hosted on [GitHub](https://github.com/stnolting/neorv32) and [opencores.org](https://opencores.org/projects/neorv32).
|
This project is hosted on [GitHub](https://github.com/stnolting/neorv32) and [opencores.org](https://opencores.org/projects/neorv32).
|
A not-so-complete project log can be found on [hackaday.io](https://hackaday.io/project/174167-the-neorv32-risc-v-processor).
|
A not-so-complete project log can be found on [hackaday.io](https://hackaday.io/project/174167-the-neorv32-risc-v-processor).
|
|
|
|
|
### Key Features
|
### Key Features
|
|
|
- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and PMP (physical memory protection) extensions
|
- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions
|
- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
|
- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
|
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
|
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
|
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
|
- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
|
- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
|
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
|
| Line 85... |
Line 85... |
|
|
* From zero to main(): Completely open source and documented.
|
* From zero to main(): Completely open source and documented.
|
* Plain VHDL without technology-specific parts like attributes, macros or primitives.
|
* Plain VHDL without technology-specific parts like attributes, macros or primitives.
|
* Easy to use – working out of the box.
|
* Easy to use – working out of the box.
|
* Clean synchronous design, no wacky combinatorial interfaces.
|
* Clean synchronous design, no wacky combinatorial interfaces.
|
* Be as small as possible – but with a reasonable size-speed tradeoff.
|
* Be as small as possible – but with a reasonable size-performance tradeoff.
|
* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
|
* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
|
|
|
|
|
### Status
|
### Status
|
|
|
| Line 103... |
Line 103... |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) |
|
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) |
|
| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
|
| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
|
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
|
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
|
|
|
|
|
### Non RISC-V-Compliant Issues
|
|
|
|
* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
|
|
* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
|
|
* `mcause` CSR is read-only
|
|
* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
|
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
|
|
|
|
|
|
### NEORV32-Specific CPU Extensions
|
|
|
|
The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
|
|
|
|
* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
|
|
|
|
|
### To-Do / Wish List
|
### To-Do / Wish List
|
|
|
- Add AXI(-Lite) bridges
|
- Add AXI(-Lite) bridges
|
- Synthesis results (+ wrappers?) for more platforms
|
- Synthesis results (+ wrappers?) for more platforms
|
- Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
|
- Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
|
- Implement further CPU extensions:
|
- Implement further CPU extensions:
|
- Atomic operations (`A`)
|
- Atomic operations (`A`)
|
|
- Bitmanipulation operations (`B`), when they are "official"
|
- Floating-point instructions (`F`)
|
- Floating-point instructions (`F`)
|
- ...
|
- ...
|
|
|
|
|
## Features
|
## Features
|
|
|
### Processor Features
|
### Processor Features
|
|
|
|
|
|
|
Highly customizable processor configuration:
|
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
|
- Optional processor-internal data and instruction memories (DMEM/IMEM)
|
is highly customizable via the processor top's generics.
|
- Optional internal bootloader with UART console and automatic SPI flash boot option
|
|
- Optional machine system timer (MTIME), RISC-V-compliant
|
- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
|
- Optional universal asynchronous receiver and transmitter (UART)
|
- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
|
- Optional 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
|
- Optional machine system timer (**MTIME**), RISC-V-compliant
|
- Optional two wire serial interface controller (TWI), compatible to the I²C standard
|
- Optional universal asynchronous receiver and transmitter (**UART**)
|
- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
|
- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
|
- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
|
- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
|
- Optional watchdog timer (WDT)
|
- Optional general purpose parallel IO port (**GPIO**), 16xOut & 16xIn, with pin-change interrupt
|
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
|
- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
|
- Optional GARO-based true random number generator (TRNG)
|
- Optional watchdog timer (**WDT**)
|
- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
|
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
|
- System configuration information memory to check hardware configuration by software (SYSINFO)
|
- Optional GARO-based true random number generator (**TRNG**)
|
|
- Optional dummy device (**DEVNULL**); used for debugging; can also be used for *fast* simulation console output
|
|
- Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors
|
|
- System configuration information memory to check hardware configuration by software (**SYSINFO**)
|
|
|
### CPU Features
|
### CPU Features
|
|
|
|
|
|
|
| Line 165... |
Line 152... |
More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
|
More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
|
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
|
**General**:
|
**General**:
|
* Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch)
|
* Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via bus I/D mux)
|
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
|
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
|
* No hardware support of unaligned accesses - they will trigger an exception
|
* No hardware support of unaligned accesses - they will trigger an exception
|
|
* Little-endian byte order
|
|
* All reserved or unimplemented instructions will raise an illegal instruction exception
|
* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
|
* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
|
|
|
|
|
**RV32I base instruction set** (`I` extension):
|
**RV32I base instruction set** (`I` extension):
|
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
|
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
|
| Line 197... |
Line 186... |
**Privileged architecture / CSR access** (`Zicsr` extension):
|
**Privileged architecture / CSR access** (`Zicsr` extension):
|
* Privilege levels: `M-mode` (Machine mode)
|
* Privilege levels: `M-mode` (Machine mode)
|
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
|
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
|
* System instructions: `MRET` `WFI`
|
* System instructions: `MRET` `WFI`
|
* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
|
* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
|
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid` `mzext`(custom)
|
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
|
* Supported exceptions and interrupts:
|
* Supported exceptions and interrupts:
|
* Misaligned instruction address
|
* Misaligned instruction address
|
* Instruction access fault
|
* Instruction access fault
|
* Illegal instruction
|
* Illegal instruction
|
* Breakpoint (via `ebreak` instruction)
|
* Breakpoint (via `ebreak` instruction)
|
| Line 220... |
Line 209... |
|
|
**Privileged architecture / FENCE.I** (`Zifencei` extension):
|
**Privileged architecture / FENCE.I** (`Zifencei` extension):
|
* System instructions: `FENCE.I`
|
* System instructions: `FENCE.I`
|
|
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
* Additional machine CSRs: `pmpcfgx` `pmpaddrx`
|
* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
|
|
|
|
|
|
### Non-RISC-V-Compliant Issues
|
|
|
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime
|
|
* `mcause` CSR is read-only
|
|
* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
|
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
|
|
* All invalid, unimplemented, unspecified or disabled instructions will trigger an illegal instruction exception
|
|
|
|
|
|
### NEORV32-Specific CPU Extensions
|
|
|
|
The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
|
|
|
|
* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
|
|
|
|
|
|
## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
### NEORV32 CPU
|
|
|
|
This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
of the CPU's generics is assumed (e.g., no PMP). No constraints were used at all.
|
of the CPU's generics is assumed (e.g., no PMP). No constraints were used at all.
|
|
|
### CPU
|
|
|
|
Results generated for hardware version: `1.3.6.5`
|
Results generated for hardware version: `1.3.6.5`
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
|
|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
|
| `rv32i` | 1113 | 479 | 2048 | 0 | 109 MHz |
|
| `rv32i` | 1113 | 479 | 2048 | 0 | 109 MHz |
|
| `rv32i` + `Zicsr` + `Zifencei` | 1851 | 817 | 2048 | 0 | 100 MHz |
|
| `rv32i` + `Zicsr` + `Zifencei` | 1851 | 817 | 2048 | 0 | 100 MHz |
|
| `rv32im` + `Zicsr` + `Zifencei` | 2462 | 1065 | 2048 | 0 | 100 MHz |
|
| `rv32im` + `Zicsr` + `Zifencei` | 2462 | 1065 | 2048 | 0 | 100 MHz |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 2714 | 1064 | 2048 | 0 | 100 MHz |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 2714 | 1064 | 2048 | 0 | 100 MHz |
|
| `rv32emc` + `Zicsr` + `Zifencei` | 2717 | 1064 | 1024 | 0 | 100 MHz |
|
| `rv32emc` + `Zicsr` + `Zifencei` | 2717 | 1064 | 1024 | 0 | 100 MHz |
|
|
|
### Processor-Internal Peripherals and Memories
|
|
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version: `1.3.6.5`
|
Results generated for hardware version: `1.3.6.5`
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
| BOOT ROM | Bootloader ROM (4kB) | 4 | 1 | 32 768 | 0 |
|
| BOOT ROM | Bootloader ROM (4kB) | 4 | 1 | 32 768 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
|
| CFU | Custom functions unit | - | - | - | - |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 |
|
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| MTIME | Machine system timer | 266 | 166 | 0 | 0 |
|
| MTIME | Machine system timer | 266 | 166 | 0 | 0 |
|
| Line 264... |
Line 273... |
| TWI | Two-wire interface | 75 | 44 | 0 | 0 |
|
| TWI | Two-wire interface | 75 | 44 | 0 | 0 |
|
| UART | Universal asynchronous receiver/transmitter | 153 | 108 | 0 | 0 |
|
| UART | Universal asynchronous receiver/transmitter | 153 | 108 | 0 | 0 |
|
| WDT | Watchdog timer | 59 | 45 | 0 | 0 |
|
| WDT | Watchdog timer | 59 | 45 | 0 | 0 |
|
|
|
|
|
### Exemplary FPGA Setups
|
### NEORV32 Processor - Exemplary FPGA Setups
|
|
|
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
|
Exemplary processor implementation results for different FPGA platforms. The processor setup uses *all provided peripherals* (but not the _CFU_),
|
no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
|
|
Results generated for hardware version: `1.4.0.0`
|
Results generated for hardware version: `1.4.0.0`
|
|
|
| Line 279... |
Line 288... |
|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:|
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:|
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imcu` + `Zicsr` + `Zifencei` + `PMP` | 4020 (18%) | 1766 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imcu` + `Zicsr` + `Zifencei` + `PMP` | 4020 (18%) | 1766 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32icu` + `Zicsr` + `Zifencei` | 4249 (80%) | 1617 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 20.25 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32icu` + `Zicsr` + `Zifencei` | 4249 (80%) | 1617 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 20.25 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imcu` + `Zicsr` + `Zifencei` + `PMP` | 2447 (12%) | 1803 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imcu` + `Zicsr` + `Zifencei` + `PMP` | 2447 (12%) | 1803 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
|
|
**Notes**
|
**_Notes_**
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
| Line 347... |
Line 356... |
|
|
|
|
|
|
## Top Entities
|
## Top Entities
|
|
|
The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
|
The top entity of the **NEORV32 Processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
(except for the TWI signals, which are of type *std_logic*).
|
(except for the TWI signals, which are of type *std_logic*).
|
|
|
The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
|
The top entity of the **NEORV32 CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
|
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
|
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
|
|
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
Detailed information regarding the signals and configuration generics can be found in
|
|
the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project), can be found
|
|
in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
|
|
|
|
|
|
### CPU
|
|
|
Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
|
```vhdl
|
|
entity neorv32_cpu is
|
|
generic (
|
|
-- General --
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
|
-- Extension Options --
|
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
|
-- Physical Memory Protection (PMP) --
|
|
PMP_USE : boolean := false; -- implement PMP?
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
|
-- Bus Interface --
|
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
|
);
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
-- instruction bus interface --
|
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
i_bus_we_o : out std_ulogic; -- write enable
|
|
i_bus_re_o : out std_ulogic; -- read enable
|
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
|
-- data bus interface --
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
|
-- system time input from MTIME --
|
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
|
-- interrupts (risc-v compliant) --
|
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
|
-- fast interrupts (custom) --
|
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
|
);
|
|
end neorv32_cpu;
|
|
```
|
|
|
|
|
### Processor
|
### Processor
|
|
|
```vhdl
|
```vhdl
|
| Line 377... |
Line 451... |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64kB
|
-- Memory configuration: Instruction memory --
|
-- Internal Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Memory configuration: Data memory --
|
-- Internal Data memory --
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- Memory configuration: External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
| Line 407... |
Line 476... |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE : boolean := true; -- implement dummy device (DEVNULL)?
|
|
IO_CFU_USE : boolean := false -- implement custom functions unit (CFU)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 450... |
Line 520... |
);
|
);
|
end neorv32_top;
|
end neorv32_top;
|
```
|
```
|
|
|
|
|
### CPU
|
|
|
|
```vhdl
|
|
entity neorv32_cpu is
|
|
generic (
|
|
-- General --
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
|
-- Extension Options --
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
|
-- Physical Memory Protection (PMP) --
|
|
PMP_USE : boolean := false; -- implement PMP?
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
|
-- Bus Interface --
|
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
|
);
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
-- instruction bus interface --
|
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
i_bus_we_o : out std_ulogic; -- write enable
|
|
i_bus_re_o : out std_ulogic; -- read enable
|
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
|
-- data bus interface --
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
|
-- system time input from MTIME --
|
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
|
-- interrupts (risc-v compliant) --
|
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
|
-- fast interrupts (custom) --
|
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
|
);
|
|
end neorv32_cpu;
|
|
```
|
|
|
|
|
|
|
|
## Getting Started
|
## Getting Started
|
|
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
|
|
| Line 530... |
Line 536... |
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
|
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
|
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain.
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
|
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
|
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
|
|
|
|
### Dowload the NEORV32 Project
|
### Dowload the NEORV32 Project
|
|
|
Get the sources of the NEORV32 Processor project. You can either download a [release](https://github.com/stnolting/neorv32/releases)
|
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
|
or get the most recent version of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip) or using `git clone` (suggested for easy project updates via `git pull`):
|
|
|
|
$ git clone https://github.com/stnolting/neorv32.git
|
$ git clone https://github.com/stnolting/neorv32.git
|
|
|
Create a new project with your FPGA design tool of choice and add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
|
folder to this project. Make sure to add them to a **new library** called `neorv32`.
|
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
|
|
|
|
|
### Create a new Hardware Project
|
### Create a new Hardware Project
|
|
|
|
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
|
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
|
|
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART, clock, reset and some GPIO output sginals are
|
|
propagated (basically, its a FPGA "hello world" example):
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output sginals are
|
|
propagated as actual entity signals. Basically, its a FPGA "hello world" example:
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_test_setup is
|
entity neorv32_test_setup is
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
| Line 574... |
Line 583... |
);
|
);
|
end neorv32_test_setup;
|
end neorv32_test_setup;
|
```
|
```
|
|
|
|
|
### Compiling and Uploading One of the Example Projects
|
### Check the Toolchain
|
|
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
|
`sw/example/blink_led` and run:
|
`sw/example/blink_led` and run:
|
|
|
neorv32/sw/example/blink_led$ make check
|
neorv32/sw/example/blink_led$ make check
|
|
|
|
|
|
### Compiling an Example Program
|
|
|
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
|
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
|
executable `neorv32_exe.bin` in the same folder.
|
*executable* `neorv32_exe.bin` in the same folder:
|
|
|
|
neorv32/sw/example/blink_led$ make clean_all exe
|
|
|
neorv32/sw/example/blink_led$ make clean_all compile
|
|
|
|
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
### Upload the Executable via the Bootloader
|
|
|
|
Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
uses the following default UART configuration:
|
uses the following default UART configuration:
|
|
|
- 19200 Baud
|
- 19200 Baud
|
- 8 data bits
|
- 8 data bits
|
- 1 stop bit
|
- 1 stop bit
|
- No parity bits
|
- No parity bits
|
- No transmission / flow control protocol (raw bytes only)
|
- No transmission / flow control protocol (raw bytes only)
|
- Newline on `\r\n` (carriage return & newline)
|
- Newline on `\r\n` (carriage return & newline) - also for sent data
|
|
|
Use the bootloader console to upload the `neorv32_exe.bin` file and run your application image.
|
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
|
|
|
```
|
```
|
<< NEORV32 Bootloader >>
|
<< NEORV32 Bootloader >>
|
|
|
BLDV: Jul 6 2020
|
BLDV: Jul 6 2020
|
| Line 636... |
Line 651... |
|
|
|
|
## Contribute
|
## Contribute
|
|
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
|
to open a [new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line (mailto:stnolting@gmail.com).
|
to [open a new issue](https://github.com/stnolting/neorv32/issues) or directly [drop me a line](mailto:stnolting@gmail.com).
|
|
|
If you'd like to contribute:
|
If you'd like to contribute:
|
|
|
1. [Fork](https://github.com/stnolting/neorv32/fork) this repository
|
1. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork
|
2. Create a feature branch in your fork: `git checkout -b cool_new_feature`
|
2. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch`
|
3. Commit your modifications: `git commit -am 'This is awesome because ...'`
|
3. Create a new remote for the upstream repo: `git remote add https://github.com/stnolting/neorv32`
|
4. Push to the branch: `git push origin cool_new_feature`
|
3. Commit your modifications: `git commit -m "Awesome new feature!"`
|
|
4. Push to the branch: `git push origin awesome_new_feature_branch`
|
5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
|
5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
|
|
|
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
|
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
|
|
|
|
|
| Line 701... |
Line 717... |
link in question.
|
link in question.
|
|
|
|
|
#### Proprietary Notice
|
#### Proprietary Notice
|
|
|
"Windows" is a trademark of Microsoft Corporation.
|
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
|
|
"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
|
"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
|
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
|
| Line 719... |
Line 733... |
|
|
## Acknowledgements
|
## Acknowledgements
|
|
|
[](https://riscv.org/)
|
[](https://riscv.org/)
|
|
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
|
|
[](https://travis-ci.com/stnolting/neorv32)
|
[](https://travis-ci.com/stnolting/neorv32)
|
|
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
|
