| Line 130... |
Line 130... |
- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
|
- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
|
- Optional machine system timer (**MTIME**), RISC-V-compliant
|
- Optional machine system timer (**MTIME**), RISC-V-compliant
|
- Optional universal asynchronous receiver and transmitter (**UART**)
|
- Optional universal asynchronous receiver and transmitter (**UART**)
|
- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
|
- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
|
- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
|
- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
|
- Optional general purpose parallel IO port (**GPIO**), 16xOut & 16xIn, with pin-change interrupt
|
- Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
|
- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
|
- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
|
- Optional watchdog timer (**WDT**)
|
- Optional watchdog timer (**WDT**)
|
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
|
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
|
- Optional GARO-based true random number generator (**TRNG**)
|
- Optional GARO-based true random number generator (**TRNG**)
|
- Optional dummy device (**DEVNULL**); used for debugging; can also be used for *fast* simulation console output
|
- Optional dummy device (**DEVNULL**); used for debugging; can also be used for *fast* simulation console output
|
| Line 170... |
Line 170... |
|
|
**Compressed instructions** (`C` extension):
|
**Compressed instructions** (`C` extension):
|
* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
|
* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
|
* System instructions: `C.EBREAK` (only with `Zicsr` extension)
|
|
|
**Embedded CPU version** (`E` extension):
|
**Embedded CPU version** (`E` extension):
|
* Reduced register file (only the 16 lowest registers)
|
* Reduced register file (only the 16 lowest registers)
|
|
|
**Integer multiplication and division hardware** (`M` extension):
|
**Integer multiplication and division hardware** (`M` extension):
|
| Line 254... |
Line 254... |
### NEORV32 Processor-Internal Peripherals and Memories
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version: `1.3.6.5`
|
Results generated for hardware version: `1.3.6.5`
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
|:----------|:-----------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
| BOOT ROM | Bootloader ROM (4kB) | 4 | 1 | 32 768 | 0 |
|
| BOOT ROM | Bootloader ROM (default 4kB) | 4 | 1 | 32 768 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
| CFU | Custom functions unit | - | - | - | - |
|
| CFU | Custom functions unit | - | - | - | - |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| DMEM | Processor-internal data memory (default 8kB) | 12 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 |
|
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| IMEM | Processor-internal instruction memory (default 16kb) | 7 | 2 | 131 072 | 0 |
|
| MTIME | Machine system timer | 266 | 166 | 0 | 0 |
|
| MTIME | Machine system timer | 266 | 166 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
|
| SPI | Serial peripheral interface | 198 | 125 | 0 | 0 |
|
| SPI | Serial peripheral interface | 198 | 125 | 0 | 0 |
|
| SYSINFO | System configuration information memory | 10 | 9 | 0 | 0 |
|
| SYSINFO | System configuration information memory | 10 | 9 | 0 | 0 |
|
| TRNG | True random number generator | 105 | 93 | 0 | 0 |
|
| TRNG | True random number generator | 105 | 93 | 0 | 0 |
|
| Line 564... |
Line 564... |
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
|
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output sginals are
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output sginals are
|
propagated as actual entity signals. Basically, its a FPGA "hello world" example:
|
propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_test_setup is
|
entity neorv32_test_setup is
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
