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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
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on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
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**[NEORV32 CPU](#CPU-Features)**
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### [NEORV32 CPU](#CPU-Features)
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The CPU implements an `rv32i RISC-V` core with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and
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The CPU implements an `rv32i RISC-V` core with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and
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`PMP` (physical memory protection) extensions. It passes the official [RISC-V compliance tests](https://github.com/stnolting/neorv32_riscv_compliance)
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`PMP` (physical memory protection) extensions. It passes the official [RISC-V compliance tests](https://github.com/stnolting/neorv32_riscv_compliance)
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and is compliant to the *Unprivileged ISA Specification [Version 2.2](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)*
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and is compliant to the *Unprivileged ISA Specification [Version 2.2](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)*
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and a subset of the *Privileged Architecture Specification [Version 1.12-draft](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)*.
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and a subset of the *Privileged Architecture Specification [Version 1.12-draft](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)*.
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If you do not want to use the NEORV32 Processor setup, you can also use the CPU in
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If you do not want to use the NEORV32 Processor setup, you can also use the CPU in
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stand-alone mode and build your own SoC around it.
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stand-alone mode and build your own SoC around it.
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**[NEORV32 Processor](#Processor-Features)**
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### [NEORV32 Processor](#Processor-Features)
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Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system
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Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system
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that already provides common peripherals like GPIO, serial interfaces, timers, embedded
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that already provides common peripherals like GPIO, serial interfaces, timers, embedded
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memories and an external bus interface for connectivity and custom extension.
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memories and an external bus interface for connectivity and custom extension.
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All optional features and modules beyond the base CPU can be enabled and configured via
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All optional features and modules beyond the base CPU can be enabled and configured via
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makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and
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makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and
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even a builtin bootloader for easy program upload via UART.
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even a builtin bootloader for easy program upload via UART.
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All software source files provide a doxygen-based documentary (available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)).
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All software source files provide a doxygen-based documentary (available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)).
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**[How to get started?](Getting-Started)**
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### [How to get started?](Getting-Started)
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The processor is intended to work "out of the box". Just synthesize the
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The processor is intended to work "out of the box". Just synthesize the
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[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
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[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
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with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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**Privileged architecture / CSR access** (`Zicsr` extension):
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
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* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Supported exceptions and interrupts:
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Misaligned instruction address
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* Instruction access fault
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* Instruction access fault
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* Illegal instruction
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* Illegal instruction
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### Non-RISC-V-Compliant Issues
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### Non-RISC-V-Compliant Issues
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime
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* `mcause` CSR is read-only
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* `mcause` CSR is read-only
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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### NEORV32-Specific CPU Extensions
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### NEORV32-Specific CPU Extensions
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BLDV: Jul 6 2020
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BLDV: Jul 6 2020
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HWV: 1.0.1.0
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HWV: 1.0.1.0
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CLK: 0x0134FD90 Hz
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CLK: 0x0134FD90 Hz
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USER: 0x0001CE40
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USER: 0x0001CE40
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MISA: 0x42801104
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MISA: 0x42801104
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CONF: 0x03FF0035
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PROC: 0x03FF0035
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IMEM: 0x00010000 bytes @ 0x00000000
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IMEM: 0x00010000 bytes @ 0x00000000
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DMEM: 0x00010000 bytes @ 0x80000000
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DMEM: 0x00010000 bytes @ 0x80000000
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Autoboot in 8s. Press key to abort.
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Autoboot in 8s. Press key to abort.
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Aborted.
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Aborted.
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