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## Introduction
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## Introduction
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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ISA Specification Version 2.1** and the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories peripherals and custom IP can be attached via a
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interrupt controller, timers and embedded memories. External memories peripherals and custom IP can be attached via a
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime and Lattice Radiant/Synplify) and can successfully execute all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example).
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## Features
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## Features
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### Processor Features
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### Processor Features
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/Makefile)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doygen_makefile_sw) documentation of the software framework
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Small hardware footprint and high operating frequency
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- Highly customizable processor configuration
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- Highly customizable processor configuration
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- Optional watchdog timer (WDT)
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- Optional watchdog timer (WDT)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- Optional GARO-based true random number generator (TRNG)
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- Optional GARO-based true random number generator (TRNG)
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- Optional core-local interrupt controller with 8 channels (CLIC)
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- Optional core-local interrupt controller with 8 channels (CLIC)
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- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
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### CPU Features
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### CPU Features
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The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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RV32I base instruction set (**`I` extension**):
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Branches instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Branches instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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Compressed instructions (**`C` extension**):
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**Compressed instructions** (`C` extension):
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Branches instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Branches instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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Embedded CPU version (**`E` extension**):
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**Embedded CPU version** (`E` extension):
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* Reduced register file (only the 16 lowest registers)
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* Reduced register file (only the 16 lowest registers)
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* No performance counter CSRs
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* No performance counter CSRs
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Integer multiplication and division hardware (**`M` extension**):
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**Integer multiplication and division hardware** (`M` extension):
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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Privileged architecture (**`Zicsr` extension**):
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**Privileged architecture** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
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* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mtinst` `mimpid` `mhartid`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mtinst` `mimpid` `mhartid`
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* Environment call from M-mode
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* Environment call from M-mode
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* Machine software instrrupt
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* Machine software instrrupt
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* Machine timer interrupt (from MTIME)
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* Machine timer interrupt (from MTIME)
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* Machine external interrupt (via CLIC)
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* Machine external interrupt (via CLIC)
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General:
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**General**:
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* No hardware support of unaligned accesses (except for instructions in `C` extension that still have to be aligned on 16-bit boundaries)
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* No hardware support of unaligned accesses (except for instructions in `C` extension that still have to be aligned on 16-bit boundaries)
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* Multi-cycle in-order instruction execution
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* Multi-cycle in-order instruction execution
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More information including a detailed list of the available CSRs can be found in
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More information including a detailed list of the available CSRs can be found in
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Peripherals / Others
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### Peripherals / Others
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| DEVNULL | Dummy device | 2 | 1 | 0 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| GPIO | General purpose input/output ports | 37 | 33 | 0 | 0 |
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| GPIO | General purpose input/output ports | 37 | 33 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| MTIME | Machine system timer | 369 | 168 | 0 | 0 |
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| MTIME | Machine system timer | 369 | 168 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 77 | 69 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 77 | 69 | 0 | 0 |
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := false -- implement true random number generator (TRNG)?
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IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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## Contact
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## Contact
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If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kinf of feedback, open a
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If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a
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[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
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[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
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stnolting@gmail.com
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stnolting@gmail.com
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